參數(shù)資料
型號(hào): CY7C057V-12AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static
中文描述: 32K X 36 DUAL-PORT SRAM, 12 ns, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFP-144
文件頁數(shù): 6/26頁
文件大?。?/td> 713K
代理商: CY7C057V-12AXC
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 14 of 26
Notes
39. CE0 = HIGH and CE1 = LOW for the duration of the above timing (both write and read cycle).
40. I/O0R = I/O0L = LOW (request semaphore); CE0R = CE0L = HIGH and CE1R = CE1L=LOW.
41. Semaphores are reset (available to both ports) at cycle start.
42. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Switching Waveforms (continued)
tSOP
tSAA
VALID ADRESS
tHD
DATAIN VALID
DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA
tPWE
tSWRD
tDOE
WRITE CYCLE
READ CYCLE
OE
R/W
I/O0
SEM
A0–A2
Semaphore Read After Write Timing, Either Side[39]
MATCH
tSPS
MATCH
R/WL
SEM L
R/WR
SEMR
Timing Diagram of Semaphore Contention[40, 41, 42]
A0L–A2L
A0R–A2R
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