- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295353 > CY7C057V-15BBXC (CYPRESS SEMICONDUCTOR CORP) 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static PDF資料下載
參數(shù)資料
| 型號： | CY7C057V-15BBXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| 中文描述： | 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172 |
| 封裝： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大小： | 713K |
| 代理商： | CY7C057V-15BBXC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 3 of 26
Functional Description
The CY7C056V and CY7C057V are low-power CMOS 16K and
32K x 36 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 36-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 72-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 72-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
logic.
Application
areas
include
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE)[3],
Read or Write Enable (R/W), and Output Enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic Power-down feature is controlled independently on
each port by Chip Select (CE0 and CE1) pins.
The CY7C056V and CY7C057V are available in 144-Pin Thin
quad plastic flatpack (TQFP) and 172-Ball ball grid array (BGA)
packages.
Note
3. CE is LOW when CE0 VIL and CE1 VIH.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C057V-15AXI | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| CY7C057V-15AXC | 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static |
| CY7C0832V-167AXC | 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120 |
| CY7C0851AV-133AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C0830AV-133AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133AI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 1M-Bit 64K x 18 4.4ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C0830AV-133BBI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C0830AV-167AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。