參數(shù)資料
型號: CY7C057V-15BBXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static
中文描述: 32K X 36 DUAL-PORT SRAM, 15 ns, PBGA172
封裝: 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, BGA-172
文件頁數(shù): 8/26頁
文件大小: 713K
代理商: CY7C057V-15BBXC
CY7C056V
CY7C057V
Document #: 38-06055 Rev. *E
Page 16 of 26
Note
44. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Switching Waveforms (continued)
ADDRESS MATCH
tPS
tBLC
tBHC
ADDRESS MATCH
tPS
tBLC
tBHC
CER Valid First:
ADDRESSL,R
BUSYR
CE0L, CE1L
CE0R, CE1R
BUSYL
ADDRESSL,R
Busy Timing Diagram No. 1 (CE Arbitration)[44]
CHIP SELECT VALID
CE0L, CE1L
CE0R, CE1R
CHIP SELECT VALID
CEL Valid First:
ADDRESS MATCH
tPS
ADDRESSL
BUSYR
ADDRESS MISMATCH
tRC or tWC
tBLA
tBHA
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
BUSR
tRC or tWC
tBLA
tBHA
ADDRESSR
Right Address Valid First:
Busy Timing Diagram No. 2 (Address Arbitration)[44]
Left Address Valid First:
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