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參數(shù)資料
| 型號(hào)： | CY7C1062AV25-10BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 32 Static RAM |
| 中文描述： | 512K X 32 STANDARD SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | CY7C1062AV25-10BGI |
CY7C1062AV25
Document #: 38-05333 Rev. *A
Page 4 of 9
AC Switching Characteristics
Over the Operating Range
[4]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Description
–10
Unit
Min.
Max.
V
CC
(typical) to the first access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
, CE
2
,
or CE
3
LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[6]
OE HIGH to High-Z
[6]
CE
1
, CE
2
,
or CE
3
LOW to Low-Z
[6]
CE
1
, CE
2
,
or CE
3
HIGH to High-Z
[6]
CE
1
, CE
2
,
or CE
3
LOW to Power-up
[7]
CE
1
, CE
2
,
or CE
3
HIGH to Power-down
[7]
Byte Enable to Data Valid
Byte Enable to Low-Z
[6]
Byte Disable to High-Z
[6]
1
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
3
10
5
1
5
3
5
0
10
5
1
5
Write Cycle Time
CE
1
, CE
2
, or CE
3
LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[6]
WE LOW to High-Z
[6]
Byte Enable to End of Write
10
7
7
0
0
7
5.5
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
7
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified
I
/I
and transmission line loads. Test conditions for the read cycle use output loading as shown in (a) of AC Test Loads, unless specified otherwise.
5. This part has a voltage regulator that steps down the voltage from 2.3V to 2V internally. t
power
time has to be provided initially before a read/write operation is
started.
6. t
, t
, t
, t
, and t
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
± 200 mV from steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE 2 HIGH, CE3 LOW, and WE LOW. The chip enables must be active and WE
must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced
to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY7C1062AV33-10BGC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K x 32 Fast Async COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-10BGCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K x 32 Fast Async COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-10BGI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K x 32 Fast Async IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-10BGIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K x 32 Fast Async IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062AV33-12BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 3.3V 16M-Bit 512K x 32 12ns 119-Pin BGA |
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