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參數(shù)資料
| 型號(hào)： | CY7C1062DV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16-Mbit (512K X 32) Static RAM |
| 中文描述： | 16兆位（512k × 32的）靜態(tài)RAM |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 310K |
| 代理商： | CY7C1062DV33 |
PRELIMINARY
CY7C1062DV33
Document #: 38-05477 Rev.*C
Page 4 of 10
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in (a) of AC Test Loads, unless specified otherwise.
6. t
gives the minimum amount of time that the power supply should be at typical V
values until the first memory access can be performed.
7. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE
1
and CE
2
and CE
3
LOW. When deselect HIGH, CE indicates the
CE
1
or CE
2
or CE
3
HIGH
8. t
, t
, t
, t
, and t
LZOE
, t
LZCE
, t
LZWE
, and t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±
200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10.The internal write time of the memory is defined by the overlap of CE
LOW, CE
LOW, CE
LOW and WE LOW. The chip enables must be active and WE must
be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Description
–10
Unit
Min.
Max.
V
CC
(typical) to the first access
[6]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
active LOW to Data Valid
[7]
OE LOW to Data Valid
OE LOW to Low-Z
[8]
OE HIGH to High-Z
[8]
CE
active LOW to Low-Z
[7, 8]
CE deselect
HIGH to High-Z
[7, 8]
CE
active LOW to Power-up
[7, 9]
CE deselect
HIGH to Power-down
[7, 9]
Byte Enable to Data Valid
Byte Enable to Low-Z
[8]
Byte Disable to High-Z
[8]
100
10
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
3
10
5
1
5
3
5
0
10
5
1
5
Write Cycle Time
CE
active LOW LOW to Write End
[7]
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[8]
WE LOW to High-Z
[8]
Byte Enable to End of Write
10
7
7
0
0
7
5.5
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
7
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY7C1062DV33-10BGI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 16-Mbit (512K x 32) 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062DV33-10BGIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 16Mb 512Kx32 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062DV33-10BGXES | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1062DV33-10BGXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 BGA 119 10ns 16Mb RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1062DV33-10BGXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 16Mbit 10ns 119-BGA |
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