參數(shù)資料
型號(hào): CY7C1069AV33-10BAC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 2M x 8 Static RAM
中文描述: 2M X 8 STANDARD SRAM, 10 ns, PBGA60
封裝: 8 X 20 MM, 1.20 MM HEIGHT, FBGA-60
文件頁數(shù): 11/12頁
文件大小: 460K
代理商: CY7C1069AV33-10BAC
CY7C1069AV33
Document #: 38-05255 Rev. *G
Page 8
Figure 7. Write Cycle No. 1 (CE1 Controlled)[16, 17, 18]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW)[16, 17, 18]
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
t
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
DATA I/O
ADDRESS
CE
WE
tSA
tLZWE
tHZWE
Truth Table
CE1
CE2
OE
WE
I/O0–I/O7
Mode
Power
H
X
High-Z
Power Down
Standby (ISB)
X
L
X
High-Z
Power Down
Standby (ISB)
L
H
L
H
Data Out
Read All Bits
Active (ICC)
L
H
X
L
Data In
Write All Bits
Active (ICC)
L
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Notes
16. Data I/O is high-impedance if OE = VIH.
17. If CE1 goes HIGH/CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.
18. CE above is defined as a combination of CE1 and CE2. It is active low.
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