參數(shù)資料
型號: CY7C1168V18-333BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 1M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 2/27頁
文件大小: 648K
代理商: CY7C1168V18-333BZXC
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 10 of 27
Write Cycle Descriptions
The write cycle descriptions of CY7C1166V18 and CY7C1168V18 follows. [2, 8]
BWS0/
NWS0
BWS1/
NWS1
K
Comments
L
L–H
During the Data portion of a write sequence
:
CY7C1166V18
both nibbles (D
[7:0]) are written into the device.
CY7C1168V18
both bytes (D
[17:0]) are written into the device.
L
L-H During the Data portion of a write sequence
:
CY7C1166V18
both nibbles (D
[7:0]) are written into the device.
CY7C1168V18
both bytes (D
[17:0]) are written into the device.
L
H
L–H
During the Data portion of a write sequence
:
CY7C1166V18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1168V18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the Data portion of a write sequence
:
CY7C1166V18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1168V18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the Data portion of a write sequence
:
CY7C1166V18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1168V18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the Data portion of a write sequence
:
CY7C1166V18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1168V18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L–H
No data is written into the devices during this portion of a write operation.
H
L–H No data is written into the devices during this portion of a write operation.
The write cycle descriptions of CY7C1177V18 follows. [2, 8]
BWS0
K
Comments
L
L-H
During the Data portion of a Write sequence
, the single byte (D
[8:0]) is written into the device.
L
L-H
During the Data portion of a Write sequence
, the single byte (D
[8:0]) is written into the device.
H
L-H
No data is written into the device during this portion of a Write operation.
H
L-H
No data is written into the device during this portion of a Write operation.
Note
8. Is based on a write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 on different
portions of a write cycle, as long as the setup and hold requirements are achieved.
相關(guān)PDF資料
PDF描述
CY7C1168V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-300BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-300BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-300BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1170V18-300BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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CY7C1168V18-375BZXC 功能描述:靜態(tài)隨機存取存儲器 18M Q2+, B2 (2.5) RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1168V18-400BZC 功能描述:靜態(tài)隨機存取存儲器 18M Q2+, B2 (2.5) RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1168V18-400BZCES 制造商:Cypress Semiconductor 功能描述:
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