參數(shù)資料
型號: CY7C1177V18-300BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
中文描述: 2M X 9 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 16/27頁
文件大?。?/td> 648K
代理商: CY7C1177V18-300BZI
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D
Page 23 of 27
Switching Waveform
Read/Write/Deselect Sequence
Figure 7. Waveform for 2.5 Cycle Read Latency[28, 29]
1
2
3
4
5
6
7
89
10
READ
NOP
WRITE
t
NOP
11
LD
R/W
A
tKH tKL
tCYC
tHC
tSA tHA
DON’T CARE
UNDEFINED
SC
A0
A1
A2
A3
A4
CQ
K
QVLD
t
NOP
DQ
K
tCCQO
tCQOH
tCCQO
tCQOH
QVLD
t
QVLD
t
QVLD
t
KHKH
12
READ
(Read Latency = 2.5 Cycles)
NOP
tCLZ
tCHZ
CQDOH
Q00
Q11
Q01 Q10
tDOH
tCO
Q40
tSD
HD
tSD
tHD
D20 D21
D30
D31
t
tCQD
t
tCQH
tCQHCQH
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
相關(guān)PDF資料
PDF描述
CY7C1177V18-300BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-300BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1177V18-333BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
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