參數(shù)資料
型號(hào): CY7C1337
廠商: Cypress Semiconductor Corp.
英文描述: 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM)
中文描述: 32K的× 32同步流水線緩存內(nèi)存(32K的× 32同步流水線式高速緩沖存儲(chǔ)器的RAM)
文件頁(yè)數(shù): 15/17頁(yè)
文件大?。?/td> 321K
代理商: CY7C1337
CY7C1337
PRELIMINARY
Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Switching Waveforms
(continued)
Read/Write Cycle Timing
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data-
In/Out
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADS
t
ADH
t
ADVS
t
ADVH
RD1
WD2
RD3
t
AH
t
AS
t
WS
t
WH
t
WH
t
WS
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
t
OELZ
t
CO
t
DOE
3a
Out
3c
Out
3d
Out
t
OEHZ
t
DOH
T
CHZ
Single Read
Burst Read
Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE
= UNDEFINED
Pipelined Read
WE is the combination of BWE & BW
to define
a write cycle (see write cycle definition table).
2a
In
3b
Out
Single Write
t
DS
t
DH
2a
Out
See Note
Note: Write data forwarded to outputs on read immediately following a write
相關(guān)PDF資料
PDF描述
CY7C1338G-117AXI 4-Mbit (128K x 32) Flow-Through Sync SRAM
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參數(shù)描述
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