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參數(shù)資料
| 型號： | CY7C1337 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM) |
| 中文描述： | 32K的× 32同步流水線緩存內存（32K的× 32同步流水線式高速緩沖存儲器的RAM） |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 321K |
| 代理商： | CY7C1337 |
CY7C1337
PRELIMINARY
5
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (T
CO
) is 5.0 ns
(117MHz device). A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automati-
cally increments the address for the rest of the burst access.
The CY7C1337 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the processor ad-
dress strobe (ADSP) or the controller address strobe (ADSC).
Address advancement through the burst sequence is con-
trolled by the ADV input.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[0-3]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous chip selects (CE
1
, CE
2
, CE
3
) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output three-state control. ADSP is ignored if CE
1
is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write sig-
nals (GW, BWE) are all deasserted HIGH. ADSP is ignored if
CE
1
is HIGH. The address presented to the address inputs
(A
0
-A
14
) is stored into the address advancement logic and the
Address Register while being presented to the memory core.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 5.0 ns(117MHz device) if OE is active
low. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
0
-A
14
is loaded into the address register and the address
advancement logic while being delivered to the RAM core.
The write signals (GW, BWE, and BW
0
–BW
3
) and ADV inputs
are ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise,
the data presented to the DQ
0
–DQ
31
inputs is written into the
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
[3:0]
signals. The CY7C1337 provides byte write capability
that is described in the write cycle description table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW
0
- BW
3
) input will selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will remain unaltered. A Synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
Because the CY7C1337 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
0
-DQ
31
inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ
0
-DQ
31
are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
0
- BW
3
) are asserted active to conduct a write
to the desired byte(s). ADSC triggered write accesses require
a single clock cycle to complete. The address presented to
A
0
-A
14
is loaded into the address register and the address
advancement logic while being delivered to the RAM core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQ
0
-DQ
31
is written into
the corresponding address location in the RAM core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain unal-
tered. A Synchronous self-timed write mechanism has been
provided to simplify the write operations.
Because the CY7C1337 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
0
-DQ
31
inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ
0
-DQ
31
are automatically
three-stated whenever a write cycle is detected, regardless of
the state of OE.
Burst Sequences
The CY7C1337 provides a two-bit wraparound counter, fed by
A
0
and A
1
, that implements either an interleaved or linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
00
11
10
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
10
01
00
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1338B-100AC | 功能描述:IC SRAM 4MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 |
| CY7C1338B-100ACT | 制造商:Cypress Semiconductor 功能描述:Cache Mem 4M-Bit 3.3V SRAM 100-Pin TQFP T/R |
| CY7C1338B-100AXC | 制造商: 功能描述: 制造商:undefined 功能描述: |
| CY7C1338B-100BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1338B-100BGCT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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