參數(shù)資料
型號(hào): CY7C1337
廠商: Cypress Semiconductor Corp.
英文描述: 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM)
中文描述: 32K的× 32同步流水線緩存內(nèi)存(32K的× 32同步流水線式高速緩沖存儲(chǔ)器的RAM)
文件頁(yè)數(shù): 6/17頁(yè)
文件大?。?/td> 321K
代理商: CY7C1337
CY7C1337
PRELIMINARY
6
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. While in
this mode, data integrity is guaranteed. Accesses pending
when entering the “sleep” mode are not considered valid nor
is the completion of the operation guaranteed. The device
should be deselected prior to entering the “sleep” mode. CE
1
,
CE
2
, CE
3,
ADSP, and ADSC must remain inactive for the du-
ration of t
ZZREC
after the ZZ input returns low.
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
I
CCZZ
Snooze mode standby
current
ZZ > V
DDQ
0.2V
2
mA
I
CCZZ
( L version)
Snooze mode standby
current
ZZ > V
DDQ
0.2V
500
μ
A
t
ZZS
Device operation to ZZ
ZZ > V
DDQ
0.2V
3t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ < 0.2V
3t
CYC
ns
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