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參數(shù)資料
| 型號： | CY7C1339 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 32 Synchronous-Pipelined Cache RAM(128K x 32 同步流水線式高速緩沖存儲器 RAM) |
| 中文描述： | 128K的× 32同步流水線緩存內(nèi)存（128K的× 32同步流水線式高速緩沖存儲器的RAM） |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 277K |
| 代理商： | CY7C1339 |
CY7C1339
3
Pin Definitions
Pin Number
50
–
44, 81,
82, 99, 100,
32
–
37
96
–
93
Name
A
[16:0]
I/O
Input-
Description
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and
CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[3:0]
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if
CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of
a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-
matically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When assert-
ed LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE
1
is deserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When assert-
ed LOW, A
[16:0]
is captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
“
sleep
”
Input. This active HIGH input places the device in a non-time-critical
“
sleep
”
condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[16:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
are placed in a three-state
condition.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power
supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
BW
[3:0]
Input-
Synchronous
Input-
Synchronous
88
GW
87
BWE
Input-
Synchronous
Input-Clock
89
CLK
98
CE
1
Input-
Synchronous
97
CE
2
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
92
CE
3
86
OE
83
ADV
Input-
Synchronous
Input-
Synchronous
84
ADSP
85
ADSC
Input-
Synchronous
64
ZZ
Input-
Asynchronous
I/O-
Synchronous
29, 28, 25-22,
19, 18,13,12,
9
–
6, 3, 2, 79,
78, 75
–
72,
69, 68, 63, 62
59
–
56, 53, 52
15, 41, 65, 91
DQ
[31:0]
V
DD
Power Supply
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
31
V
SS
V
DDQ
Ground
I/O Power
Supply
I/O Ground
V
SSQ
MODE
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When tied
to V
DDQ
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation.
No Connects.
1, 14, 16, 30,
38, 39, 42, 43,
51, 66, 80
NC
-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1339-166AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1339A-100AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:4MB (128K X 32 )- BURST SYNCHROUNOUS PIPELINE SRAM - Bulk 制造商:Cypress Semiconductor 功能描述:128KX32 4M PIPELINE 3.3V CACHE 100.000 MHZ |
| CY7C1339A-100ACT | 制造商:Cypress Semiconductor 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel |
| CY7C1339A-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1339A-83AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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