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參數(shù)資料
| 型號(hào)： | CY7C1339 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 32 Synchronous-Pipelined Cache RAM(128K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| 中文描述： | 128K的× 32同步流水線緩存內(nèi)存（128K的× 32同步流水線式高速緩沖存儲(chǔ)器的RAM） |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | CY7C1339 |
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CY7C1339
9
AC Test Loads and Waveforms
OUTPUT
R=317
R=351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
=50
Z
0
=50
V
L
= 1.5V
3.3V
ALL INPUT PULSES
[10]
2.5V
GND
90%
10%
90%
10%
≤
2.5ns
≤
2.5ns
(c)
Switching Characteristics
Over the Operating Range
[11,12,13]
-166
-133
-100
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
CYC
Clock Cycle Time
6.0
7.5
10
ns
t
CH
Clock HIGH
1.7
1.9
3.5
ns
t
CL
Clock LOW
1.7
1.9
3.5
ns
t
AS
Address Set-Up Before CLK Rise
2.0
2.5
2.5
ns
t
AH
Address Hold After CLK Rise
0.5
0.5
0.5
ns
t
CO
Data Output Valid After CLK Rise
3.5
4.0
5.5
ns
t
DOH
Data Output Hold After CLK Rise
1.5
2.0
2.0
ns
t
ADS
ADSP, ADSC Set-Up Before CLK Rise
2.0
2.5
2.5
ns
t
ADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
ns
t
WES
BWE, GW, BW[3:0] Set-Up Before CLK Rise
2.0
2.5
2.5
ns
t
WEH
BWE, GW, BW[3:0] Hold After CLK Rise
0.5
0.5
0.5
ns
t
ADVS
ADV Set-Up Before CLK Rise
2.0
2.5
2.5
ns
t
ADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
ns
t
DS
Data Input Set-Up Before CLK Rise
2.0
2.5
2.5
ns
t
DH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
t
CES
Chip Select Set-Up
2.0
2.5
2.5
ns
t
CEH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
ns
t
CHZ
Clock to High-Z
[12]
3.5
3.5
3.5
ns
t
CLZ
Clock to Low-Z
[12]
OE HIGH to Output High-Z
[12, 13]
0
0
0
ns
t
EOHZ
3.5
3.5
5.5
ns
t
EOLZ
OE LOW to Output Low-Z
[12, 13]
0
0
0
ns
t
EOV
OE LOW to Output Valid
[12]
3.5
4.0
5.5
ns
Notes:
10. Input waveform should have a slew rate of 1V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified I
/I
OH
and load capacitance. Shown in (a) and (b) of AC test loads.
12. t
, t
CLZ
, t
EOV
, t
EOLZ
, and t
EOHZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mf from steady-state
voltage.
13. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1339-166AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1339A-100AC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:4MB (128K X 32 )- BURST SYNCHROUNOUS PIPELINE SRAM - Bulk 制造商:Cypress Semiconductor 功能描述:128KX32 4M PIPELINE 3.3V CACHE 100.000 MHZ |
| CY7C1339A-100ACT | 制造商:Cypress Semiconductor 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:4M- 128KX32 3.3V PIPELINE 1CD-SYNCHRONOUS SRAM - Tape and Reel |
| CY7C1339A-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1339A-83AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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