參數(shù)資料
型號: CY7C1362B-225BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
中文描述: 512K X 18 CACHE SRAM, 2.8 ns, PBGA165
封裝: 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
文件頁數(shù): 20/34頁
文件大?。?/td> 895K
代理商: CY7C1362B-225BZI
CY7C1360B
CY7C1362B
Document #: 38-05291 Rev. *C
Page 20 of 34
Identification Register Definitions
Instruction Field
CY7C1360B
(256KX36)
CY7C1362B
(512KX18)
Description
Revision Number (31:29)
001
001
Describes the version number
Device Depth (28:24)
01010
01010
Reserved for Internal Use
Device Width (23:18)
000000
000000
Defines memory type and architecture
Cypress Device ID (17:12)
100110
010110
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of SRAM vendor
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size(x36)
Bit Size(x18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order
71
71
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
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