參數(shù)資料
型號: CY7C1371BV25-83BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 36 ZBT SRAM, 10 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁數(shù): 10/25頁
文件大小: 709K
代理商: CY7C1371BV25-83BGC
CY7C1373BV25
CY7C1371BV25
Document #: 38-05250 Rev. *A
Page 18 of 25
tALH
ADV/LD Hold after CLK Rise
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
ns
Switching Characteristics Over the Operating Range (continued)[18]
Parameter
Description
117
100
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Switching Waveforms
CEN
CLK
ADDRESS
CE
WE
Data
In/Out
tCYC
tCH tCL
tCENS
tCENH
RA1
tAH
tAS
tWES
tWEH
tCES
tCEH
tCDV
Q4
Q1
= DON’T CARE
= UNDEFINED
WE is the combination of WE and BWSx(x = a, b, c, d) to define a write cycle (see Write Cycle Description table).
Out
D2
In
D5
In
Out
Re
a
d
Wr
it
e
DES
E
L
E
CT
Wr
it
e
Re
a
d
Re
a
d
Re
a
d
S
u
spe
n
d
Re
a
d
DESEL
ECT
DESEL
ECT
WA2
RA3
RA4
WA5
RA6
RA7
tCLZ
tDOH
Q3
Out
tCHZ
CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select
the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for
Device
originally
deselected
Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
Q7
Out
tCHZ
tCENS
tCENH
tDOH
Q6
Out
Read/Write/Deselect Sequence
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