參數(shù)資料
型號(hào): CY7C1371BV25-83BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 36 ZBT SRAM, 10 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁(yè)數(shù): 4/25頁(yè)
文件大?。?/td> 709K
代理商: CY7C1371BV25-83BGC
CY7C1373BV25
CY7C1371BV25
Document #: 38-05250 Rev. *A
Page 12 of 25
TAP Controller Block Diagram
0
1
2
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
x
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
TAP Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = 4.0 mA
2.0
V
VOH2
Output HIGH Voltage
IOH = 100 A
VDD0.2
V
VOL1
Output LOW Voltage
IOL = 8.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 A
0.2
V
VIH
Input HIGH Voltage
1.7
VDD+0.3
V
VIL
Input LOW Voltage
0.3
0.7
V
IX
Input Load Current
GND
≤ V
I ≤ VDDQ
5
A
Notes:
8.
All Voltage referenced to Ground.
9.
Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot:VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200 ms.
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Min.
Max
Unit
tTCYC
TCK Clock Cycle Time
100
ns
tTF
TCK Clock Frequency
10
MHz
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
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