參數(shù)資料
型號(hào)： CY7C1381D-133AXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述： 512K X 36 CACHE SRAM, 6.5 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù)： 13/29頁(yè)
文件大?。?/td> 975K
代理商： CY7C1381D-133AXI
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Document #: 38-05544 Rev. *F
Page 13 of 29
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
[10, 11]
Parameter
Description
Min
Max
Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Setup Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
ns
20
20
20
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
Notes:
10.t
and t
refer to the setup and hold time requirements of latching data from the boundary scan register.
11.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
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相關(guān)PDF資料
PDF描述
CY7C1381D-133BZI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-133BZXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381F-100BGC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381F-100BGI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1381D-133AXIT 功能描述:IC SRAM 18MBIT 133MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1381D-133BGC 制造商:Cypress Semiconductor 功能描述:
CY7C1381D-133BGXC 功能描述:IC SRAM 18MBIT 133MHZ 165LFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1381D-133BZI 制造商:Cypress Semiconductor 功能描述:
CY7C1381DV25-133AXC 制造商:Cypress Semiconductor 功能描述:
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