參數(shù)資料
型號(hào)： CY7C1381D-133AXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述： 512K X 36 CACHE SRAM, 6.5 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 975K
代理商： CY7C1381D-133AXI
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Document #: 38-05544 Rev. *F
Page 15 of 29
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
[13]
Device Width (23:18) 119-BGA
CY7C1381D/CY7C1381F
(512K × 36)
000
01011
101001
CY7C1383D/CY7C1383F
(1M × 18)
000
01011
101001
Description
Describes the version number.
Reserved for internal use.
Defines the memory type and
architecture.
Defines the memory type and
architecture.
Defines the width and density.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID
register.
Device Width (23:18) 165-FBGA
000001
000001
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
100101
00000110100
010101
00000110100
ID Register Presence Indicator (0)
1
1
Scan Register Sizes
Register Name
Bit Size (×36)
3
1
32
85
89
Bit Size (×18)
3
1
32
85
89
Instruction Bypass
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to High-Z state.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use. This instruction is reserved for future use.
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Note:
13.Bit #24 is “1” in the register definitions for both 2.5V and 3.3V versions of this device.
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1381D-133BZI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381D-133BZXI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381F-100BGC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381F-100BGI 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1381D-133AXIT 功能描述:IC SRAM 18MBIT 133MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1381D-133BGC 制造商:Cypress Semiconductor 功能描述:
CY7C1381D-133BGXC 功能描述:IC SRAM 18MBIT 133MHZ 165LFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2
CY7C1381D-133BZI 制造商:Cypress Semiconductor 功能描述:
CY7C1381DV25-133AXC 制造商:Cypress Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*