參數(shù)資料
型號(hào)： CY7C1442AV25-200BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 2M X 18 CACHE SRAM, 3.2 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 4264K
代理商： CY7C1442AV25-200BZC
CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Document #: 38-05350 Rev. *E
Page 16 of 32
Identification Register Definitions
Instruction Field
CY7C1440AV25
(1M x36)
CY7C1442AV25
(2M x18)
CY7C1446AV25
(512K x72)
Description
Revision Number (31:29)
000
Describes the version number.
Device Depth (28:24)
01011
Reserved for Internal Use
Architecture/Memory Type(23:18)
000000
Defines memory type and architecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (165-ball FBGA package)
89
–
Boundary Scan Order (209-ball FBGA package)
–
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
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