- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378507 > CY7C1470V25-167AXC (CYPRESS SEMICONDUCTOR CORP) 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture PDF資料下載
參數(shù)資料
| 型號： | CY7C1470V25-167AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 2M X 36 ZBT SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 20/27頁 |
| 文件大?。?/td> | 382K |
| 代理商： | CY7C1470V25-167AXC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
PRELIMINARY
CY7C1470V25
CY7C1472V25
CY7C1474V25
Document #: 38-05290 Rev. *E
Page 20 of 27
Switching Characteristics
Over the Operating Range
[15, 16]
Parameter
t
Power[17]
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
OEV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Shaded areas contain advance information.
Description
-250
-200
-167
Unit
ms
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
V
CC
(typical) to the First Access Read or Write
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
4.0
5.0
6.0
ns
MHz
ns
ns
250
200
167
2.0
2.0
2.0
2.0
2.2
2.2
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
[18, 19, 20]
Clock to Low-Z
[18, 19, 20]
OE HIGH to Output High-Z
[18, 19, 20]
OE LOW to Output Low-Z
[18, 19, 20]
3.0
3.0
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
1.3
1.3
1.5
3.0
3.0
3.4
1.3
1.3
1.5
3.0
3.0
3.4
0
0
0
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BW
x
Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
x
Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
15.Timing reference is 1.25V when V
= 2.5V and 0.9V when V
= 1.8V.
16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
17.This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
18.t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20.This parameter is sampled and not 100% tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1470V33-167AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1470V33-250BZXC | ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80% |
| CY7C1470V33-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1470V33-167BZXC | ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80% |
| CY7C1470V33-167BZXI | RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 05V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1470V25-167AXCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 3.4NS 100TQFP - Bulk |
| CY7C1470V25-167AXCT | 功能描述:靜態(tài)隨機存取存儲器 2Mx36 2.5V NoBL PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1470V25-167BZC | 功能描述:靜態(tài)隨機存取存儲器 72MB (2Mx36) 2.5v 167MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1470V25-167BZCT | 功能描述:靜態(tài)隨機存取存儲器 2Mx36 2.5V NoBL PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1470V25-167BZI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 3.4NS 165FBGA - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。