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參數(shù)資料
| 型號： | CY7C1470V25-167AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL⑩ Architecture |
| 中文描述： | 2M X 36 ZBT SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 382K |
| 代理商： | CY7C1470V25-167AXC |
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PRELIMINARY
CY7C1470V25
CY7C1472V25
CY7C1474V25
Document #: 38-05290 Rev. *E
Page 6 of 27
ADV/LD
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address
.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock Input
. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device.
Output Enable, active LOW
. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
Clock Enable Input, active LOW
. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
[18:0]
during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
a
–DQ
h
are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines
. Functionally, these signals are identical to DQ
[71:0]
. During
write sequences, DQP
a
is controlled by BW
a
, DQP
b
is controlled by BW
b
, DQP
c
is controlled by
BW
c
, and DQP
d
is controlled by BW
d
, DQP
e
is controlled by BW
e,
DQP
f
is controlled by BW
f,
DQP
g
is controlled by BW
g,
DQP
h
is controlled by BW
h
.
Mode Input
. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of TCK.
CLK
Input-
Clock
Input-
CE
1
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
2
CE
3
OE
CEN
Input-
Synchronous
DQ
s
I/O-
Synchronous
DQP
X
I/O-
Synchronous
MODE
Input Strap Pin
TDO
JTAG Serial
Output
Synchronous
JTAG Serial Input
Synchronous
Test Mode Select
Synchronous
JTAG Clock
Power Supply
I/O Power Supply
Power supply for the I/O circuitry
.
Ground
Ground for the device
. Should be connected to ground of the system.
–
No connects
. This pin is not connected to the die.
–
These pins are not connected
. They will be used for expansion to the 144M and 288M densities.
TDI
Serial data-In to the JTAG circuit
. Sampled on the rising edge of TCK.
TMS
This pin controls the Test Access Port state machine
. Sampled on the rising edge of TCK.
TCK
V
DD
V
DDQ
V
SS
NC
E(144,
288)
ZZ
Clock input to the JTAG circuitry
.
Power supply inputs to the core of the device
.
Input-
Asynchronous
ZZ “Sleep” Input
. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to V
SS
or left
floating.
Pin Definitions
(continued)
Pin Name
I/O Type
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1470V33-167AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1470V33-250BZXC | ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80% |
| CY7C1470V33-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1470V33-167BZXC | ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80% |
| CY7C1470V33-167BZXI | RS-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 05V; Power: 2W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protection; Low Noise; No External Capacitor needed; Efficiency to 83% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1470V25-167AXCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 3.4NS 100TQFP - Bulk |
| CY7C1470V25-167AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx36 2.5V NoBL PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1470V25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 72MB (2Mx36) 2.5v 167MHz 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1470V25-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx36 2.5V NoBL PL 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1470V25-167BZI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 2.5V 72MBIT 2MX36 3.4NS 165FBGA - Bulk |
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