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參數(shù)資料
| 型號： | CY7C166-15VC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 16K x 4 Static RAM |
| 中文描述： | 16K X 4 STANDARD SRAM, 15 ns, PDSO24 |
| 封裝： | 0.300 INCH, MO-088, SOJ-24 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 525K |
| 代理商： | CY7C166-15VC |
CY7C166
Document #: 38-05025 Rev. *C
Page 7 of 12
Write Cycle No. 1(WE Controlled)[11,12]
Write Cycle No. 2(CE Controlled)[11,12,13]
Notes
11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
12. CY7C166 only: Data I/O will be high-impedance if OE = VIH.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Switching Waveforms (continued)
tWC
DATA UNDEFINED
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
tHZWE
tLZWE
tSD
DATAINVALID
CE
WE
DATA IN
DATA I/O
ADDRESS
tWC
HIGH IMPEDANCE
tSCE
tAW
tSA
tPWE
tHA
tHD
tSD
DATAIN VALID
ADDRESS
CE
DATA IN
DATA I/O
WE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C166 | 16K x 4 Static RAM |
| CY7C199-35VIT | 32K X 8 STANDARD SRAM, 35 ns, PDSO28 |
| CY7C276-25QMB | x16 EPROM |
| CY7C276-30HC | EPROM|16KX16|CMOS|LDCC|44PIN|CERAMIC |
| CY7C276-30HMB | x16 EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C166-15VCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C16620DC | 制造商:CYPRESS 功能描述:* |
| CY7C166-20PC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C166-20VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C16620VCT | 制造商:CYPRESS 功能描述:* |
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