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參數(shù)資料
| 型號(hào)： | CY7C166-15VC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 16K x 4 Static RAM |
| 中文描述： | 16K X 4 STANDARD SRAM, 15 ns, PDSO24 |
| 封裝： | 0.300 INCH, MO-088, SOJ-24 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 525K |
| 代理商： | CY7C166-15VC |
CY7C166
Document #: 38-05025 Rev. *C
Page 5 of 12
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range[4]
CY7C166-15
Parameter
Description
Min
Max
Unit
READ CYCLE
tRC
Read cycle time
15
–
ns
tAA
Address to data valid
–
15
ns
tOHA
Output hold from address change
3
–
ns
tACE
CE LOW to data valid
–
15
ns
tDOE
OE LOW to data valid
–
10
ns
tLZOE
OE LOW to low Z
3
–
ns
tHZOE
OE HIGH to high Z
–
8
ns
tLZCE
CE LOW to low Z[5]
3
–
ns
tHZCE
CE HIGH to high Z[5, 6]
–
8
ns
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
15
ns
WRITE CYCLE[7]
tWC
Write cycle time
15
–
ns
tSCE
CE LOW to write end
12
–
ns
tAW
Address set-up to write end
12
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address set-up to write start
0
–
ns
tPWE
WE pulse width
12
–
ns
tSD
Data set-up to write end
10
–
ns
tHD
Data hold from write end
0
–
ns
tLZWE
WE HIGH to low Z[5]
5
–
ns
tHZWE
WE LOW to high Z[5, 6]
–
7
ns
Notes
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 30 pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured 500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3.0 V
5 V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5ns
< 5 ns
5 V
OUTPUT
R1 481
R2
255
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73 V
Equivalent to:
THVENIN EQUIVALENT
ALL INPUT PULSES
C164–5
167
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PDF描述 |
|---|---|
| CY7C166 | 16K x 4 Static RAM |
| CY7C199-35VIT | 32K X 8 STANDARD SRAM, 35 ns, PDSO28 |
| CY7C276-25QMB | x16 EPROM |
| CY7C276-30HC | EPROM|16KX16|CMOS|LDCC|44PIN|CERAMIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C166-15VCT | 制造商:Cypress Semiconductor 功能描述: |
| CY7C16620DC | 制造商:CYPRESS 功能描述:* |
| CY7C166-20PC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C166-20VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C16620VCT | 制造商:CYPRESS 功能描述:* |
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