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參數(shù)資料
| 型號(hào)： | CY7C2561KV18-450BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 8M X 8 QDR SRAM, 0.37 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.4 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 839K |
| 代理商： | CY7C2561KV18-450BZC |
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PRELIMINARY
CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Document Number: 001-15887 Rev. *E
Page 10 of 29
Application Example
Figure 1 shows two QDR-II+ used in an application.
Figure 1. Application Example
Table 3. Truth Table
The truth table for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follows. [4, 5, 6, 7, 8, 9]
Operation
K
RPS WPS
DQ
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L-H
↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Read Cycle:
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and
half cycles; read data on
two consecutive K and K
rising edges.
L-H
L [11]
XQ(A) at K(t + 2)
↑ Q(A + 1) at K(t + 3)↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4)↑
NOP: No Operation
L-H
H
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
X
Previous State
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Vt
R
D
A
K
SRAM #2
RQ = 250 ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
D
A
K
SRAM #1
RQ = 250 ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
RPS
WPS
BWS
CLKIN1/CLKIN1
R = 50ohms, Vt = V
/2
DDQ
R
ODT
R
CLKIN2/CLKIN2
Notes
4. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑represents rising edge.
5. Device powers up deselected with the outputs in a tri-state condition.
6. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
7. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
8. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
9. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
10. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
11. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
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