- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379097 > CY8C22113 (Cypress Semiconductor Corp.) PSoC Mixed Signal Array PDF資料下載
參數(shù)資料
| 型號： | CY8C22113 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | PSoC混合信號陣列 |
| 文件頁數(shù)： | 226/304頁 |
| 文件大?。?/td> | 2956K |
| 代理商： | CY8C22113 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁當前第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁
18. Analog Interface
CY8C22xxx Preliminary Data Sheet
226
Document No. 38-12009 Rev. *D
December 22, 2003
18.1.4
Decimator and Incremental ADC
Interface
The Decimator and Incremental interface provides hardware
support and signal routing for analog-to-digital conversion
functions, specifically the Delta-Signal ADC and the Incre-
mental ADC. The control signals for this interface is split
between two registers: DEC_CR0 and DEC_CR1.
18.1.4.1
Decimator
The decimator is a hardware block that is used to perform
digital processing on the analog block outputs. The DCLKS0
and DCLKS1 bits, which are split between the DEC_CR0
and DEC_CR1 registers, are used to select a source for the
Decimator output latch enable. The Decimator is typically
run autonomously over a given period. The length of this
period is set in a Timer block that is running in conjunction
with the analog processing. At the terminal count of this
Timer, the primary output goes high for a one-half clock
cycle. For purposes of Decimator operation, this signal is
inverted and connected to the BW input. This becomes the
output latch enable signal, which transfers data from the
internal accumulators to an output buffer. The terminal count
also causes an interrupt and the CPU may read this output
buffer at any time between one latch event and the next.
18.1.4.2
Incremental ADC
The analog interface has support for the incremental ADC
operation through the ability to gate the analog comparator
outputs. This gating function is required in order to precisely
control the digital integration period that is performed in a
digital block, as part of the function. A digital block PWM is
used as a source to provide the gate signal. Only one
source for the gating signal can be selected. However, the
gating can be applied independently to any of the column
comparator outputs.
The ICLKS0 and ICLKS1 bits, which are split between the
DEC_CR0 and DEC_CR1 registers, are used to select a
source for the incremental gating signal. The four IGEN bits
are used to independently enable the gating function on a
column-by-column basis.
18.1.5
Analog Modulator Interface (Mod
Bits)
The Analog Modulator Interface provides a selection of sig-
nals that are routed to any of the four analog array modula-
tion control signals. There is one modulation control signal
for each Type C Analog Switched Capacitor block in every
analog column. There are eight selections, which include
the analog comparator bus outputs, two global outputs, and
a digital block broadcast bus. The selections for all columns
are identical and are contained in the AMD_CR0 and
AMD_CR1 registers. The Mod bit is XOR’ed with the
Switched Capacitor block Sign bit (ASign in ASCxxCR0) to
provide dynamic control of that bit.
18.1.6
Analog Synchronization Interface
(Stalling)
For high precision analog operation, it is necessary to pre-
cisely time when updated register values are available to the
analog PSOC blocks. The optimum time to update values in
Switch Cap registers is at the beginning of the PHI1 active
period. Depending on the relationship between the CPU
CLK and the analog column clock, the CPU IO write cycle
can occur at any 24 MHz master clock boundary in the PHI1
or PHI2 cycle. Register values may be written at arbitrary
times; however, glitches may be apparent at analog outputs.
This is because the capacitor value is changing when the
circuit is designed to be settling.
The SYNCEN bit in the Analog Synchronization Control
Register (ASY_CR) is designed to address this problem.
When the SYNCEN bit is set, an IO write instruction to any
Switch Cap registers is blocked at the interface and the CPU
will stall. On the subsequent rising edge of PHI1, the CPU
stall is released, allowing the IO write to be performed at the
destination analog register. This mode synchronizes the IO
write action to be performed at the optimum point in the ana-
log cycle, at the expense of CPU bandwidth.
Figure 18-4
shows the timing for this operation.
Figure 18-4. Synchronized Write to a DAC Register
As an alternative to stalling, the source for the analog col-
umn interrupts is set as the falling edge of the PHI2 clock.
This configuration synchronizes the CPU to perform the IO
write after the PHI2 phase is completed, which is equivalent
to the start of PHI1.
18.1.7
SAR Hardware Acceleration
The SAR algorithm is a binary search on the DAC code that
best matches the input voltage that is being measured. The
first step is to take an initial guess at mid-scale, which effec-
tively splits the range by half. The DAC output value is then
compared to the input voltage. If the guess is too low, a
result bit is set for that binary position and the next guess is
set at mid-scale of the remaining upper range. If the guess
is too high, a result bit is cleared and the next guess is set at
mid-scale of the remaining lower range. This process is
repeated until all bits are tested. The resulting DAC code is
CPUCLK
(Generated)
CPUCLK
(To CPU)
IOW
STALL
PHI
CLK24
AIOW
Stall is released here.
AIOW
completes here.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY8C22113-24PI | PSoC Mixed Signal Array |
| CY8C22113-24SI | PSoC Mixed Signal Array |
| CY8C22213 | PSoC Mixed Signal Array |
| CY8C22213-24LFI | PSoC Mixed Signal Array |
| CY8C22213-24PI | PSoC Mixed Signal Array |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY8C22113_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC⑩ Mixed Signal Array |
| CY8C22113-24PI | 功能描述:IC MCU 2K FLASH 256B 8-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標準包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22113-24SI | 功能描述:IC MCU 2K FLASH 256B 8-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標準包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22113-24SIT | 功能描述:IC MCU 2K FLASH 256B 8-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:PSOC®1 CY8C22xxx 標準包裝:60 系列:BlueStreak ; LH7 核心處理器:ARM7 芯體尺寸:32-位 速度:84MHz 連通性:EBI/EMI，SPI，SSI，SSP，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):76 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:32K x 8 電壓 - 電源 (Vcc/Vdd):1.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 |
| CY8C22213 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PSoC⑩ Mixed Signal Array |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。