參數(shù)資料
型號: CY8C24794-SPC
廠商: Cypress Semiconductor Corp.
英文描述: PSoCTM Mixed-Signal Array
中文描述: PSoCTM混合信號陣列
文件頁數(shù): 26/32頁
文件大?。?/td> 366K
代理商: CY8C24794-SPC
April 14, 2005
Document No. 38-12018 Rev. *F
26
CY8C24794 Final Data Sheet
3. Electrical Specifications
3.4.7
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
T
A
85
°
C, or 3.0V to 3.6V and -40
°
C
T
A
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Table 3-23. 5V AC Analog Output Buffer Specifications
Symbol
T
ROB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mV
pp
, 3dB BW, 100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1V
pp
, 3dB BW, 100pF Load
Power = Low
Power = High
2.5
2.5
μ
s
μ
s
T
SOB
2.2
2.2
μ
s
μ
s
SR
ROB
0.65
0.65
V/
μ
s
V/
μ
s
SR
FOB
0.65
0.65
V/
μ
s
V/
μ
s
BW
OBSS
0.8
0.8
MHz
MHz
BW
OBLS
300
300
kHz
kHz
Table 3-24. 3.3V AC Analog Output Buffer Specifications
Symbol
T
ROB
Description
Min
Typ
Max
Units
Notes
Rising Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1V Step, 100pF Load
Power = Low
Power = High
Rising Slew Rate (20% to 80%), 1V Step, 100pF Load
Power = Low
Power = High
Falling Slew Rate (80% to 20%), 1V Step, 100pF Load
Power = Low
Power = High
Small Signal Bandwidth, 20mV
pp
, 3dB BW, 100pF Load
Power = Low
Power = High
Large Signal Bandwidth, 1V
pp
, 3dB BW, 100pF Load
Power = Low
Power = High
3.8
3.8
μ
s
μ
s
T
SOB
2.6
2.6
μ
s
μ
s
SR
ROB
0.5
0.5
V/
μ
s
V/
μ
s
SR
FOB
0.5
0.5
V/
μ
s
V/
μ
s
BW
OBSS
0.7
0.7
MHz
MHz
BW
OBLS
200
200
kHz
kHz
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