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參數(shù)資料
| 型號： | CYW150OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK 440BX AGP 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器，擴展頻譜時鐘發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:33 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 150MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
CYW150
........................ Document #: 38-07177 Rev. *B Page 3 of 14
Overview
The CYW150 was designed as a single-chip alternative to the
standard two-chip Intel 440BX AGPset clock solution. It
provides sufficient outputs to support most single-processor,
four SDRAM DIMM designs.
Functional Description
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after
power-up, the logic state of each pin is latched and the pins
become clock outputs. This feature reduces device pin count
by combining clock outputs with input select pins.
An external 10-k
“strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
Figure 2 show two suggested methods for strapping resistor
connections.
Upon CYW150 power-up, the first 2 ms of operation are used
for input logic selection. During this period, the five I/O pins (2,
8, 9, 29, 30) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pins and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled, converting the l/O pins into operating clock outputs.
The 2-ms timer starts when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no signif-
icant effect on clock output signal integrity. The drive
impedance of clock output (< 40
, nominal) is minimally
affected by the 10-k
strap to ground or V
DD. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length
to minimize system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the corresponding specified output frequency is
delivered on the pins, assuming that VDD has stabilized. If VDD
has not yet reached full value, output frequency initially may
be below target but will increase to target once VDD voltage
has stabilized. In either case, a short output clock cycle may
be produced from the CPU clock outputs when the outputs are
enabled.
VDDQ2
50, 56
P
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or
3.3V.
GND
4, 10, 23,
26, 34,
42, 48, 53
G
Ground Connections: Connect all ground pins to the common system ground plane.
Pin Definitions (continued)
Pin Name
Pin No.
Pin
Type
Pin Description
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
CYW150
VDD
Clock Load
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
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