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參數(shù)資料
| 型號(hào)： | CYW150OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK 440BX AGP 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 時(shí)鐘/頻率合成器，擴(kuò)展頻譜時(shí)鐘發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:33 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 150MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
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CYW150
........................ Document #: 38-07177 Rev. *B Page 4 of 14
Spread Spectrum Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in Figure 3.
As shown in Figure 3, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the SMBus data stream. Refer to Table 7 for more details.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
CYW150
VDD
Clock Load
R
10 k
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
SSFTG
Typical Clock
Frequency Span (MHz)
–1.0
+1.0
0
–0.5%
–SS%
+SS%
Ampl
it
ude
(
d
B
)
5 dB/div
+0.5%
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| CYW152-12G | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CYW15G0101DXB | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYW15G0101DXB-BBC | 功能描述:電信線路管理 IC Sngl Ch XCVR COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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| CYW15G0101DXB-BBXC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
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