參數(shù)資料
型號: CYW15G0101DXB
廠商: Cypress Semiconductor Corp.
英文描述: Single-channel HOTLink II Transceiver(單通道熱連接II收發(fā)器)
中文描述: 單通道HOTLink II收發(fā)器(單通道熱連接二收發(fā)器)
文件頁數(shù): 1/39頁
文件大?。?/td> 450K
代理商: CYW15G0101DXB
Single-channel HOTLink II Transceiver
CYV15G0101DXB
CYW15G0101DXB
CYP15G0101DXB
Cypress Semiconductor Corporation
Document #: 38-02031 Rev. *J
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised March 24, 2005
Features
Second-generation HOTLink
technology
Compliant to multiple standards
—ESCON
, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
—CPRI compliant
—CYW15G0101DXB compliant to OBSAI-RP3
—CYV15G0101DXB compliant to SMPTE 259M and
SMPTE 292M
—8B/10B encoded or 10-bit unencoded data
Single-channel transceiver operates from 195 to
1500 MBaud serial data rate
—CYW15G0101DXB operates from 195 to 1540 MBaud
Selectable parity check/generate
Selectable input clocking options
Selectable output clocking options
MultiFrame Receive Framer
—Bit and Byte alignment
—Comma or full K28.5 detect
—Single- or Multi-Byte framer for byte alignment
—Low-latency option
Synchronous LVTTL parallel input and parallel output
interface
Internal phase-locked loops (PLLs) with no external
PLL components
Dual differential PECL-compatible serial inputs
—Internal DC-restoration
Dual differential PECL-compatible serial outputs
Source matched for driving 50
transmission lines
—No external bias resistors required
—Signaling-rate controlled edge-rates
Optional Elasticity Buffer in Receive Path
Optional Phase Align Buffer in Transmit Path
Compatible with
—Fiber-optic modules
—Copper cables
—Circuit board traces
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Per-channel Link Quality Indicator
—Analog signal detect
—Digital signal detect
Low power 1.25W @ 3.3V typical
Single 3.3V supply
100-ball BGA
Pb-Free package option available
0.25
μ
BiCMOS technology
Functional Description
The CYP(V)15G0101DXB
[1]
single-channel HOTLink II
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. The receive channel accepts serial data and
converts it to parallel data, frames the data to character bound-
aries, decodes the framed characters into data and special
characters, and presents these characters to an Output
Register.
Figure 1
illustrates typical connections between
independent
host
systems
CYP(V)(W)15G0101DXB parts. As a second-generation
HOTLink device, the CYP(V)(W)15G0101DXB extends the
HOTLink II family with enhanced levels of integration and
faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices.
and
corresponding
Note:
1.
CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum
operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and
also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices.
10
10
10
10
Serial Link
C
S
S
Backplane or Cabled
Connections
Figure 1. HOTLink II System Connections
C
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