參數(shù)資料
型號(hào): CYW15G0101DXB
廠商: Cypress Semiconductor Corp.
英文描述: Single-channel HOTLink II Transceiver(單通道熱連接II收發(fā)器)
中文描述: 單通道HOTLink II收發(fā)器(單通道熱連接二收發(fā)器)
文件頁數(shù): 24/39頁
文件大?。?/td> 450K
代理商: CYW15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
CYP15G0101DXB
Document #: 38-02031 Rev. *J
Page 24 of 39
AC Test Loads and Waveforms
V
OLC
Output LOW Voltage
(V
CC
referenced)
100
differential load
150
differential load
100
differential load
150
differential load
V
CC
1.4
V
CC
1.4
450
560
V
CC
0.7
V
CC
0.7
900
1000
V
V
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
mV
mV
Differential Serial Line Receiver Inputs: IN1
±
, IN2
±
V
DIFFS [19]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
V
COM [21, 22]
Common Mode Input Range
100
1200
V
CC
mV
V
V
μA
μA
V
V
CC
– 2.0
V
IN
=V
IHE
Max.
V
IN
=V
ILE
Min.
1350
–700
V
CC
1.95 V
CC
0.05
Power Supply
I
CC
Typ.
[24]
390
Max.
[23]
500
510
500
510
Unit
mA
mA
mA
mA
Power Supply Current
REFCLK= Max.
Commercial
Industrial
Commercial
Industrial
I
CC
Power Supply Current
REFCLK= 125 MHz
390
DC Electrical Characteristics
Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
CYP(V)(W)15G0101DXB AC Characteristics
Over the Operating Range
Parameter
Transmitter LVTTL Switching Characteristics
f
TS
TXCLK Clock Frequency
t
TXCLK
TXCLK Period
t
TXCLKH[29]
TXCLK HIGH Time
t
TXCLKL[29]
TXCLK LOW Time
t
TXCLKR[29, 30, 31]
TXCLK Rise Time
Notes:
21. The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
22. Not applicable for AC-coupled interfaces. For AC-coupled interfaces, V
DIFFS
requirement still needs to be satisfied.
23. Maximum I
CC
is measured with V
CC
=
MAX, with all Serial Drivers enabled, parallel outputs unloaded, sending a alternating 01 pattern to the Serial Input Receiver.
24. Typical I
is measured under similar conditions except with V
=
3.3V, T
=
25°C, parallel outputs unloaded, RXCKSEL
=
MID, and with one Serial Line
Driver sending a continuous alternating 01 pattern to the Serial Input Receiver.
25. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 5pF differential load reflects tester capacitance,
and is recommended at low data rates only.
26. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses this threshold voltage.
27. This parameter is 154 MHz for CYW15G0101DXB.
28. This parameter is 6.49 ns for CYW15G0101DXB.
29. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
30. The ratio of rise time to falling time must not vary by greater than 2:1.
31. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
Description
Min.
Max.
Unit
19.5
6.66
[28]
2.2
2.2
0.2
150
[27]
51.28
MHz
ns
ns
ns
ns
1.7
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
3.0V
V
th
= 1.4V
270 ps
270 ps
[26]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
R2 = 435
C
L
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
1 ns
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[25]
[25]
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