參數(shù)資料
型號： CYW305OXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Frequency Controller with System Recovery for Intel Integrated Core Logic
中文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, LEAD FREE, SSOP-56
文件頁數(shù)： 1/21頁
文件大?。?/td> 247K
代理商： CYW305OXC
Frequency Controller with System Recovery
for Intel
Integrated Core Logic
W305B
Cypress Semiconductor Corporation
Document #: 38-07262 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised September 1, 2004
Features
Single chip FTG solution for Intel Solano/810E/810
Programmable clock output frequency with less than
1 MHz increment
Integrated fail-safe Watchdog timer for system
recovery
Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
Support SMBus byte read/write and block read/write
operations to simplify system BIOS development
Vendor ID and Revision ID support
Programmable drive strength for SDRAM and PCI
output clocks
Programmable output skew between CPU, AGP, PCI
and SDRAM
Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
Low jitter and tightly controlled clock skew
Two copies of CPU clock
Thirteen copies of SDRAM clock
Eight copies of PCI clock
One copy of synchronous APIC clock
Three copies of 66-MHz outputs
Three copies of 48-MHz outputs
One copy of double strength 14.31818-MHz reference
clock
One RESET output for system recovery
SMBus interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH or LOW.
Block Diagram
Pin Configuration
[1]
VDDQ3
VDDQ2
PCI1/FS1
PCI2/FS2
XTAL
OSC
PLL REF FREQ
PLL 1
X2
X1
REF2X/FS3
PCI3:7
48MHz/FS4
24_48MHz/SEL24_48MHz#
PLL2
VDDQ3
SMBus
Logic
SCLK
3V66_0:2
PCI0/FS0
CPU0:1
APIC
Divider,
Delay,
and
Phase
Control
Logic
3
VDDQ3
2
SDRAM0:12
13
RST#
/2
(FS0:4)
5
48MHz
GND
VDDQ3
REF2X/FS3^
X1
X2
VDDQ3
3V66_0
3V66_1
3V66_2
GND
PCI0/FS0^
PCI1/FS1^
PCI2/FS2^
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz
48MHz/FS4^
24_48MHz/SEL24_48MHz#*
W
VDDQ2
APIC
GND
VDDQ2
CPU0
CPU1
GND
SDRAM0
SDRAM1
SDRAM2
VDDQ3
GND
SDRAM3
SDRAM4
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
SDRAM10
VDDQ3
GND
SDRAM11
SDRAM12
RST#
SCLK
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
28
VDDQ3
SDATA
GND
VDDQ3
相關(guān)PDF資料
PDF描述
CYW305OXCT Frequency Controller with System Recovery for Intel Integrated Core Logic
CYWUSB6935 WirelessUSB LR 2.4-GHz DSSS Radio SoC(WirelessUSB LR 2.4-GHz DSSS無線SoC)
CZA1414P Video Switch Compatible With IIC Bus(IIC總線控制的視頻轉(zhuǎn)換芯片)
D-BY228G Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free TQFP; Pins: 144; Temperature: AUTO; LUTs (k): 8
D-BYW36 Fast Silicon Rectifiers Schnelle Si-Gleichrichter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYW305OXCT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Legacy-Sys Clk Intel RSolano Chip W305B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CYW311OXC 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Sys Clk VIATM Pro266 DDR Chipset W311 DS RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CYW311OXCT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Sys Clk VIATM Pro266 DDR Chipset W311 DS RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
CYW312OXC 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency
CYW312OXCT 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*