參數(shù)資料
型號: CYW305OXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Frequency Controller with System Recovery for Intel Integrated Core Logic
中文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, LEAD FREE, SSOP-56
文件頁數(shù): 8/21頁
文件大小: 247K
代理商: CYW305OXC
W305B
Document #: 38-07262 Rev. *B
Page 8 of 21
Bit 3
15
PCI3
1
(Active/Inactive)
Bit 2
13
PCI2
1
(Active/Inactive)
Bit 1
12
PCI1
1
(Active/Inactive)
Bit 0
11
PCI0
1
(Active/Inactive)
Byte 3: Control Register 3
Bit
Pin#
Name
Default
Description
Bit 7
9
3V66_2
1
(Active/Inactive)
Bit 6
8
3V66_1
1
(Active/Inactive)
Bit 5
7
3V66_0
1
(Active/Inactive)
Bit 4
55
APIC
1
(Active/Inactive)
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
51
CPU1
1
(Active/Inactive)
Bit 0
52
CPU0
1
(Active/Inactive)
Byte 2: Control Register 2
(continued)
Bit
Pin#
Name
Default
Description
Byte 4: Control Register 4
Bit
Pin#
Name
Default
Description
Bit 7
38
SDRAM7
1
(Active/Inactive)
Bit 6
41
SDRAM6
1
(Active/Inactive)
Bit 5
42
SDRAM5
1
(Active/Inactive)
Bit 4
43
SDRAM4
1
(Active/Inactive)
Bit 3
44
SDRAM3
1
(Active/Inactive)
Bit 2
47
SDRAM2
1
(Active/Inactive)
Bit 1
48
SDRAM1
1
(Active/Inactive)
Bit 0
49
SDRAM0
1
(Active/Inactive)
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
31
SDRAM12
1
(Active/Inactive)
Bit 3
32
SDRAM11
1
(Active/Inactive)
Bit 2
35
SDRAM10
1
(Active/Inactive)
Bit 1
36
SDRAM9
1
(Active/Inactive)
Bit 0
37
SDRAM8
1
(Active/Inactive)
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