參數(shù)資料
型號: CYW305OXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: Frequency Controller with System Recovery for Intel Integrated Core Logic
中文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, LEAD FREE, SSOP-56
文件頁數(shù): 3/21頁
文件大小: 247K
代理商: CYW305OXC
W305B
Document #: 38-07262 Rev. *B
Page 3 of 21
Overview
The W305B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel
archi-
tecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Upon power-up the power on strap option pins act as a logic
input. An external 10-k
strapping resistor should be used.
Figure 1
shows a suggested method for strapping resistor
connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below
target but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
Offsets Among Clock Signal Groups
Figure 2
,
Figure 3
, and
Figure 4
represent the phase
relationship among the different groups of clock outputs from
W305B under different frequency modes.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W305B
Clock Load
Output
10 k
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 16.6-MHz
0 ns
CPU 66 Period
SDRAM 100 Period
Hub-PCI
40 ns
30 ns
20 ns
10 ns
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