24 FN6785.0 July 29, 2010 Configuration Setting The configuration mode is assigned through two pairs of pin settings. When t" />
參數(shù)資料
型號： D2-45057-QR-T
廠商： Intersil
文件頁數(shù)： 17/31頁
文件大?。?/td> 0K
描述： IC DGTL AMP PWM CTRLR 68QFN
標(biāo)準(zhǔn)包裝： 3,000
系列： D2Audio™
類型： D 類
輸出類型： 2 通道（立體聲）
在某負載時最大輸出功率 x 通道數(shù)量： 30W x 1 @ 8 歐姆
電源電壓： 9 V ~ 26 V
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
封裝/外殼： 68-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
D2-45057, D2-45157
24
FN6785.0
July 29, 2010
Configuration Setting
The configuration mode is assigned through two pairs of
pin settings. When the D2-45057, D2-45157 device exits
its reset state, the logic status of the PSSYNC/CFG1 and
nERROR/CFG0 pins is latched into internal device
registers. During this initialization time, these pins
operate as logic inputs. After completion of the
initialization and the internal firmware begins executing,
these pins are re-assigned as outputs for their shared
functions, and the internal latched logic state that defines
the configuration mode remains until the device is
powered down or reset again. The OCFG0 and OCFG1 pin
status is not latched; those pins are to remain in their
pull-up or pull-down state.
Selection of one of the four configuration modes is
defined by strapping the configuration pins high or low:
OCFG0 and OCFG1, to define the output power stage
configuration;
and nERROR/CFG0 and PSSYNC/CFG1 pins to define
the amplifier and channel configuration
These four pins are connected to either a high (+3.3V)
level or low (ground = 0) level. Connection should be
through a 10kΩ resistor, and not directly to supply or
ground.
Table 6 shows the audio processing channel
assignment, audio content, and output assignments for
each of the four configuration modes.
Both pairs of configuration setting pins (OCFG0,
OCFG1) and (PSSYNC/CFG1, nERROR/CFG0) must be
used and both must be set to the same configuration
mode.
In modes 2 and 3, the filtering for high and low pass
crossovers is applied to the audio signal flow path,
enabling the appropriate high or low pass content to be
properly filtered for the PWM output channels.
TABLE 5. MULTI-FUNCTION I/O CONTROL PIN ASSIGNMENT AND OPERATION
PIN
NAME
PIN STATE DURING
INITIALIZATION
PIN STATE DURING OPERATION
CONNECTION REFERENCE
I/O
FUNCTION
I/O
FUNCTION
TEMPREF/
SCK
Output SPI Cock Output.
Input Temperature Monitor
Reference. Used for
Temperature Monitoring
Algorithm.
Typical connection is to 49.9kΩ
resistor as temperature monitor
reference. Available for SPI connect
if SPI is used in application.
VOL1/
MISO
Input
or
Output
SPI Master Input or Slave
Output. Function (Master or
Slave) determined by nSS
input state.
Input Volume Control Phase-B
input. Used for Monitoring
Rotary-Encoder Volume
Control.
Typical connection to +3.3V with
10kΩ pull-up resistors, and to 2-bit
volume control encoder.
TEMP1/
MOSI
Output
or
Input
SPI Master Output or Slave
Input. Function (Master or
Slave) determined by nSS
input state.
I/O
Temperature monitor
reference I/O pin. Used for
Temperature Monitoring
Algorithm.
Typical connection is to 100kΩ NTC
resistor as temperature monitor
reference. Available for SPI connect
if SPI is used in application.
nERROR/
CFG0
Input (CFG0) Configuration Mode
Input Select. Uses pull-up or
pull-down to set logic input
level, to define one of 4
amplifier configurations.
Output Active-Low Output Amplifier
Protection and Monitoring
Status Indication.
Connects to +3.3V or to ground with
10 kΩ resistor, to select logic high or
low for setting configuration. Also
connects to input of monitor or
indicator circuit to provide status.
(Referenced as “PSTEMP” on some
reference designs.)
PSSYNC/
CFG1
Input (CFG1) Configuration Mode
Input Select. Uses pull-up or
pull-down to set logic input
level, to define one of 4
amplifier configurations.
Output Sync Output for
Synchronizing On-Board
Power Supply regulator.
Connects to +3.3V or to ground with
10kΩ resistor, to select logic high or
low for setting configuration. Also
connects to clock sync input of
on-board switching regulator.
(Referenced as “PSCURR” on some
reference designs.)
VOL0/
nSS
Input SPI Slave Select.
Input Volume Control Phase-A
input. Used for monitoring
rotary-encoder volume
control.
Typical connection to +3.3V with
10kΩ pull-up resistors, and to 2-bit
volume control encoder.
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