參數(shù)資料
型號(hào)： DAC1008D650HN
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： DAC
英文描述： Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
中文描述： 10-BIT DAC, PQCC64
封裝： 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁(yè)數(shù)： 79/98頁(yè)
文件大?。?/td> 551K
代理商： DAC1008D650HN
DAC1008D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 December 2010
79 of 98
NXP Semiconductors
DAC1008D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
10.15.2.12
Page 6 bit definition detailed description
Please refer to
Table 143
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 144. LN0_CFG_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN0_DID[7:0]
Access
R
Value
-
Description
lane 0 device ID
Table 145. LN0_CFG_1 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
3 to 0
LN0_BID[3:0]
Access
R
Value
-
Description
lane 0 bank ID
Table 146. LN0_CFG_2 register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN0_LID[4:0]
Access
R
Value
-
Description
lane 0 lane ID
Table 147. LN0_CFG_3 register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
7
LN0_SCR
4 to 0
LN0_L[4:0]
Access
R
R
Value
-
-
Description
scrambling on
number of lanes minus 1
Table 148. LN0_CFG_4 register (address 04h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN0_F[7:0]
Access
R
Value
-
Description
number of octets per frame minus 1
Table 149. LN0_CFG_5 register (address 05h) bit description
Default settings are shown highlighted.
Bit
Symbol
4 to 0
LN0_K[4:0]
Access
R
Value
-
Description
number of frames per multi-frame minus 1
Table 150. LN0_CFG_6 register (address 06h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 0
LN0_M[7:0]
Access
R
Value
-
Description
number of converters per device minus 1
Table 151. LN0_CFG_7 register (address 07h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 6
LN0_CS[1:0]
4 to 0
LN0_N[4:0]
Access
R
R
Value
-
-
Description
number of control bits
converter resolution minus 1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC1008D650HN/C1,5 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008D650HN-C1 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008D750 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× interpolating with JESD204A interface
DAC1008D750_11 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
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