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參數(shù)資料
| 型號(hào)： | DAC2KY |
| 英文描述： | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 雙通道，12位，125Msps數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 389K |
| 代理商： | DAC2KY |
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DAC2902
SBAS167A
12
The DC gain for this circuit is equal to feedback resistor R
F
.
At high frequencies, the DAC output impedance (C
D1
, C
D2
)
will produce a 0 in the noise gain for the OPA2680 that may
cause peaking in the closed-loop frequency response. C
F
is
added across R
F
to compensate for this noise gain peaking.
To achieve a flat transimpedance frequency response, the
pole in each feedback network should be set to:
1
2
π
R
F
C
F
=
GBP
4
π
R
F
C
D
(8)
with GBP = Gain Bandwidth Product of OPA,
which will give a corner frequency f
-3dB
of approximately:
f
3dB
=
GBP
2
π
R
F
C
D
(9)
The full-scale output voltage is simply defined by the prod-
uct of I
OUTFS
R
F
, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
R
F
and/or I
OUTFS
should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680
’
s output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single-load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50
resistor
connected to I
OUT
, providing the termination of the further
connected 50
cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25
load.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, I
OUTFS
, and the load resistor, may be mutu-
ally adjusted to provide the desired output signal swing and
performance.
INTERFACING ANALOG
QUADRATURE MODULATORS
One of the main applications for the dual-channel DAC is
baseband I- and Q-channel transmission for digital commu-
nications. In this application, the DAC is followed by an
analog quadrature modulator, modulating an IF carrier with
the baseband data, as shown in Figure 7. Often, the input
stages of these quadrate modulators consist of npn-type
transistors that require a DC bias (base) voltage of > 0.8V.
The wide output compliance range (
–
10V to +1.25V) allows
for a direct DC
–
coupling between the DAC2902 and the
quadrature modulator.
FIGURE 6. Driving a Doubly Terminated 50
Cable Directly.
FIGURE 7. Generic Interface to a Quadrature Modulator. Signal Conditioning (Level-Shifting) May Be Required to Ensure
Correct DC Common-Mode Levels At the Input of the Quadrature Modulator.
I
OUT
I
OUT
DAC2902
25
50
50
I
OUTFS
= 20mA
V
OUT
= 0V to +0.5V
I
OUT
1
I
OUT
1
I
OUT
2
I
OUT
2
DAC2902
Signal
Conditioning
I
IN
I
REF
Q
IN
Q
REF
∑
Quadrature Modulator
V
OUT
~ 0Vp to 1.20Vp
V
IN
~ 0.6Vp to 1.8Vp
RF
I
IN
I
REF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC2902 | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| DAC2902-EVM | Dual, 12-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER |
| DAC2900-EVM | DAC2900 10-bit, 125MSPS DC EVM(DAC2900 10位, 125MSPS DC 評(píng)估板) |
| DAC2902-EVM | DAC2902 12-bit, 125MSPS DC EVM(DAC2902 12位, 125MSPS DC 評(píng)估板) |
| DAC2904-EVM | DAC2904 14-bit, 125MSPS DC EVM(DAC2904 14位, 125MSPS DC 評(píng)估板) |
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