
3
DAC667
TIMING SPECIFICATIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t
DC
t
AC
t
CP
t
DH
t
SETT
Data Valid to End of CS
Address Valid to End of CS
CS Pulse Width
Data Hold Time
Output Voltage Settling Time
50
100
100
0
–
–
–
–
–
2
–
–
–
–
4
ns
ns
ns
ns
μ
s
All models, T
A
= +25
°
C, V
CC
= +12V or +15V, V
EE
= –12V or –15V.
ABSOLUTE MAXIMUM RATINGS
V
CC
to Power Ground ..............................................................0V to +18V
V
to Power Ground ..............................................................0V to –18V
Digital Inputs (Pins 11–15, 17–28) to Power Ground.............–1V to +7V
Ref In to Reference Ground..............................................................
±
12V
Bipolar Offset to Reference Ground .................................................
±
12V
10V Span Resistor to Reference Ground .........................................
±
12V
20V Span Resistor to Reference Ground .........................................
±
24V
Ref Out, V
OUT
(Pins 6, 9) ....................Indefinite Short to Power Ground,
Momentary Short To V
CC
Power Dissipation ........................................................................1000mW
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
TEMPERATURE
RANGE
LINEARITY ERROR
max at 25
°
C
±
1/2LSB
GAIN TC, max
(ppm/
°
C)
±
30
PACKAGE DRAWING
NUMBER
(1)
PRODUCT
PACKAGE
DAC667JP
28-Pin Plastic DIP
0
°
C to +70
°
C
215
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
TIMING DIAGRAMS
Load first rank from Data Bus; A3 = 1.
t
Write Cycle #1
t
SETT
CS
±1/2LSB
A3
t
AC
t
CP
Load second rank from first rank; A2, A1, A0 = 1.
Write Cycle #2
Output
CS
A2–A0
t
AC
t
DC
t
DH
t
CP
DB11–DB0