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參數(shù)資料
| 型號： | DAC667 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Microprocessor-Compatible 12-Bit Dightal-To-Analog Converter(與微處理器兼容的12位D/A轉(zhuǎn)換器) |
| 中文描述： | 微處理器兼容的12位Dightal到模擬轉(zhuǎn)換器（與微處理器兼容的12位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 218K |
| 代理商： | DAC667 |
5
DAC667
zero analog output and all ones (FFF
HEX
) gives an analog
output 1LSB below full scale.
Input coding for bipolar analog outputs is bipolar offset
binary (BOB), where an input code of 000
HEX
gives a minus
full-scale output, an input of FFF
HEX
gives an output 1LSB
below positive full scale, and zero occurs for an input code
of 800
HEX
.
The DAC667 can be used with two’s complement coding if
a logic inverter is used ahead of the MSB input (DB11).
INTERNAL/EXTERNAL REFERENCE USE
DAC667 contains a +10V reference which is trimmed to
typically
±
0.2% and tested and guaranteed to
±
1%. V
REF OUT
must be connected to V
REF IN
through a gain adjust resistor
with a nominal value of 50
. A trim potentiometer with a
nominal value of 100
can be used to provide adjustment to
zero gain error. If an external 10.000V reference is used, it
may be necessary to increase the trim range slightly.
The reference output may be used to drive external loads,
sourcing up to 5mA. The load current should be constant,
otherwise the gain (and bipolar offset, if connected) of the
converter will vary.
It is possible to use references other than +10V. The recom-
mended range of reference voltage is from +8V to +11V,
which allows both 8.192V and 10.24V ranges to be used.
The DAC667 is optimized for fixed-reference applications.
If the reference voltage is expected to vary over a wide
range, a CMOS multiplying D/A is a better choice.
GAIN AND OFFSET ADJUSTMENTS
Figures 2 and 3 illustrate the relationship of offset and gain
adjustments to a unipolar- and a bipolar-connected DAC667.
Offset should be adjusted first to avoid interaction of adjust-
ments.
FIGURE 2. Relationship of Offset and Gain Adjustments for
a Unipolar D/A Converter.
+ Full Scale
All Bits
Logic 0
1LSB
Range of
Offset Adj.
≈
±0.4%
Offset Adjust Translates the Line
Digital Input
All Bits
Logic 1
Range of
Gain Adj.
≈
±1%
A
Gain Adjust
Rotates the Line
F
+ Full Scale
All Bits
Logic 0
1LSB
Range of
Offset Adjust
Offset Adj.
Translates
the Line
≈
±0.4%
Digital Input
All Bits
Logic 1
A
Full Scale
Range
Gain Adjust
Rotates the Line
– Full Scale
MSB on All
Others Off
Bipolar
Offset
Range of
Gain Adj.
≈
±1%
Gain Adjustment
For either unipolar or bipolar operation, apply the digital
input that gives the maximum positive voltage output. Ad-
just the gain potentiometer for this positive full scale volt-
age. See Table II for calibration values.
SETTLING TIME
PERFORMANCE
The switches, reference and output amplifier of the DAC667
are designed for optimum settling time performance (Figure
4). Figure 4a shows the full scale range step response, V
OUT
–10V to +10V to –10V, for data input 000
HEX
to FFF
HEX
to
000
HEX
. Figure 4b shows the settling time response at plus
full scale (+10V) for an output transition from –10V to
+10V. Figure 4c shows the settling time response at minus
Offset Adjustment
For unipolar (USB) operation, apply the digital input code
that should produce zero voltage output and adjust the offset
potentiometer for zero output. For bipolar (BOB, BTC)
operation, apply the digital input code that produces the
maximum negative output voltage and adjust the offset
potentiometer for minus full scale voltage. See Table II for
calibration values and codes.
ANALOG OUTPUT
±
2.5V
0 to +5V
0 to +10V
±
5V
±
10V
FFF
HEX
800
HEX
7FF
HEX
000
HEX
1LSB
+4.9987V
+2.5000V
+2.4987V
0.0000V
1.22mV
+9.9976V
+5.0000V
+4.9976V
0.0000V
2.44mV
+2.4987V
0.0000V
–0.0013V
–2.5000V
1.22mV
+4.9976V
0.0000V
–0.0024V
–5.0000V
2.44mV
+9.9951V
0.0000V
–0.0049V
–10.0000V
4.88mV
DIGITAL
INPUT
TABLE II. Calibration Values.
FIGURE 3. Relationship of Offset and Gain Adjustments for
a Bipolar D/A Converter.
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