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參數(shù)資料
型號(hào): DAC8143FSZ
廠商: Analog Devices Inc
文件頁數(shù): 8/12頁
文件大小: 0K
描述: IC DAC 12BIT DAISY-CHAIN 16-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 47
設(shè)置時(shí)間: 380ns
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 500µW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 2.63M
產(chǎn)品目錄頁面: 786 (CN2011-ZH PDF)
DAC8143
–5–
REV. C
10
FREQUENCY – Hz
THD
dB
–90
0.032
THD
%
0.010
–85
–80
–75
–70
–95
0.018
0.0056
0.0032
0.0018
100
1k
10k
100k
VIN = 5V rms
OUTPUT OP AMP: OP-42
Figure 3. Multiplying Mode Total Harmonic
Distortion vs. Frequency
Typical Performance Characteristics–
ALL BITS ON
100
FREQUENCY – Hz
B10
0
ATTENUATION
dB
(MSB) B11
B9
B8
B7
B6
B5
B4
B3
B2
B1
(LSB) B0
DATA BITS "ON"
(ALL OTHER
DATA BITS "OFF")
1k
10k
100k
1M
10M
12
24
36
48
60
72
84
96
108
Figure 2. Multiplying Mode Frequency
Response vs. Digital Code
3
0
VIN – Volts
I DD
mA
2
1
0
1
234
5
Figure 4. Supply Current vs. Logic
Input Voltage
4
1
VDD – Volts
THRESHOLD
VOLTAGE
Volts
3
2
0
1
2.4
–0.8
3
5
7
9
11
13
17
15
Figure 7. Logic Threshold Voltage
vs. Supply Voltage
0.5
0
DIGITAL INPUT CODE – Decimal
LINEARITY
ERROR
LSB
0.4
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
1024
2048
3072
4095
1536
2560
3584
512
Figure 5. Linearity Error vs. Digital
Code
0.5
2
VREF – Volts
DNL
LSB
46
8
10
0.25
0
–0.25
–0.5
Figure 8. DNL Error vs. Reference
Voltage
0.5
2
VREF – Volts
INL
LSB
46
8
10
0.25
0
–0.25
–0.5
Figure 6. Linearity Error vs. Refer-
ence Voltage
40
0
SRO – VOLTAGE OUT – Volts
SINK
30
20
10
0
–10
–20
–30
–40
1
234
5
SOURCE
OUTPUT
CURRENT
mA
TA = +25 C
LOGIC 1
LOGIC 0
Figure 9. Digital Output Voltage vs.
Output Current
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