參數(shù)資料
型號: DAC8408GPZ
廠商: Analog Devices Inc
文件頁數(shù): 4/16頁
文件大小: 0K
描述: IC DAC 8BIT QUAD W/MEMORY 28DIP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 13
設置時間: 190ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 4
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.600",15.24mm)
供應商設備封裝: 28-PDIP
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): 5.26M
DAC8408
–12–
REV. A
SINGLE SUPPLY, VOLTAGE OUTPUT OPERATION
The DAC8408 can be connected with a single +5 V supply to
produce DAC output voltages from 0 V to +1.5 V. In Figure 8,
the DAC8408 R-2R ladder is inverted from its normal connec-
tion. A +1.500 V reference is connected to the current output pin
4 (IOUT 1A), and the normal VREF input pin becomes the DAC
output. Instead of a normal current output, the R-2R ladder out-
puts a voltage. The OP-490, consisting of four precision low
power op amps that can operate its inputs and outputs to zero
volts, buffers the DAC to produce a low impedance output volt-
age from 0 V to +1.5 V full-scale. Table III shows the code table.
With the supply and reference voltages as shown, better than 1/2
LSB differential and integral nonlinearity can be expected. To
maintain this performance level, the +5 V supply must not drop
below 4.75 V. Similarly, the reference voltage must be no higher
than 1.5 V. This is because the CMOS switches require a mini-
mum level of bias in order to maintain the linearity performance.
Table III. Single Supply Binary Code Table (Refer to Figure 8)
DAC Data Input
MSB
LSB
Analog Output
1 1 1 1 1 1 1 1
VREF
255
256
, +1.4941 V
1 0 0 0 0 0 0 1
VREF
129
256
, +0.7559 V
1 0 0 0 0 0 0 0
VREF
128
256
, +0.7500 V
0 1 1 1 1 1 1 1
VREF
127
256
, +0.7441 V
0 0 0 0 0 0 0 1
VREF
1
256
, +0.0059 V
0 0 0 0 0 0 0 0
VREF
0
256
, 0.0000 V
Figure 8. Unipolar Supply, Voltage Output DAC Operation
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