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參數(shù)資料
| 型號： | DAC8420QBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Quad 12-Bit Serial Voltage Output DAC |
| 中文描述： | QUAD, SERIAL INPUT LOADING, 13 us SETTLING TIME, 12-BIT DAC, UUC16 |
| 封裝： | 0.119 X 0.283 INCH, DIE-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 587K |
| 代理商： | DAC8420QBC |
DAC8420–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
SS
= –5.0 V
6
5%, V
VREFLO
= –2.5 V, –40
8
C
≤
T
A
≤
+85
8
C unless otherwise noted. See Note 1 for supply variations.)
REV. 0
–2–
(at V
DD
= +5.0 V
6
5%, V
SS
= 0.0 V, V
VREFHI
= +2.5 V, V
VREFLD
= 0.0 V, and
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC ACCURACY
Integral Linearity “E”
Integral Linearity “E”
Integral Linearity “F”
Integral Linearity “F”
Differential Linearity
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
Min-Scale Tempco
Full-Scale Tempco
INL
INL
INL
INL
DNL
ZSE
FSE
ZSE
FSE
TC
ZSE
TC
FSE
±
1/4
±
1/2
±
3/4
±
1
±
1/4
±
1
±
3
±
2
±
4
±
1
±
4
±
4
±
8
±
8
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/
°
C
ppm/
°
C
Note 2, V
SS
= 0 V
Note 2, V
SS
= 0 V
Monotonic Over Temperature
R
L
= 2 k
, V
SS
= –5 V
R
L
= 2 k
, V
SS
= –5 V
Note 2, R
L
= 2 k
, V
SS
= 0 V
Note 2, R
L
= 2 k
, V
SS
= 0 V
Note 3, R
L
= 2 k
, V
SS
= –5 V
Note 3, R
L
= 2 k
, V
SS
= –5 V
±
10
±
10
MATCHING PERFORMANCE
Linearity Matching
±
1
LSB
REFERENCE
Positive Reference Input Range
Negative Reference Input Range
Negative Reference Input Range
Reference High Input Current
Reference Low Input Current
V
VREFHI
V
VREFLO
V
VREFLO
I
VREFHI
I
VREFLO
Note 4
Note 4
Note 4, V
SS
= 0 V
Codes 000
H
, 555
H
Codes 000
H
, 555
H
, V
SS
= –5 V
V
VREFLO
+2.5
V
SS
0
–0.75
–1.0
V
DD
–2.5
V
VREFHI
–2.5
V
VREFHI
–2.5
+0.75
V
V
V
mA
mA
±
0.25
–0.6
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
I
OUT
t
S
SR
V
SS
= –5 V
to 0.01%, Note 5
10% to 90%, Note 5
–1.25
+1.25
mA
μ
s
V/
μ
s
8
1.5
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Input Capacitance
V
INH
V
INL
I
IN
C
IN
2.4
V
V
μ
A
pF
0.8
10
Note 3
13
LOGIC TIMING CHARACTERISTICS
3, 6
Data Setup Time
Data Hold
Clock Pulse Width HIGH
Clock Pulse Width LOW
Select Time
Deselect Delay
Load Disable Time
Load Delay
Load Pulse Width
Clear Pulse Width
t
DS
t
DH
t
CH
t
CL
t
CSS
t
CSH
t
LD1
t
LD2
t
LDW
t
CLRW
25
55
90
120
90
5
130
35
80
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
PSRR
I
DD
I
SS
P
DISS
0.002
4
–3
20
0.01
7
%/%
mA
mA
mW
–6
V
SS
= 0 V
35
NOTES
1
All supplies can be varied
±
5% and operation is guaranteed. Device is tested with V
DD
= +4.75 V.
2
For single-supply operation (V
VREFLO
= 0 V, V
SS
= 0 V), due to internal offset errors INL and DNL are measured beginning at code 003
H
.
3
Guaranteed but not tested.
4
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5
V
OUT
swing between +2.5 V and –2.5 V with V
DD
= 5.0 V.
6
All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7
Typical values indicate performance measured at +25
°
C.
Specifications subject to change without notice.
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