參數(shù)資料
型號(hào)： DAC8420QBC
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Quad 12-Bit Serial Voltage Output DAC
中文描述： QUAD, SERIAL INPUT LOADING, 13 us SETTLING TIME, 12-BIT DAC, UUC16
封裝： 0.119 X 0.283 INCH, DIE-16
文件頁(yè)數(shù)： 6/16頁(yè)
文件大?。?/td> 587K
代理商： DAC8420QBC
DAC8420
REV. 0
–6–
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTION
Power Supplies
VDD: Positive Supply, +5 V to +15 V.
VSS: Negative Supply, 0 V to –15 V.
GND: Digital Ground.
CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with
CS
.
(All are CMOS/TTL compatible.)
CLR
: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur-
rent state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of
CLR
. If HIGH, a Clear command will set the internal DAC registers A-D to
midscale (800
H
). If LOW, the registers are set to zero (000
H
).
CS
: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD
: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of
LD
, independent of
CS
. Input data
must remain stable while
LD
is LOW.
(All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when
CS
is HIGH.
The format of the 16-bit serial word is:
(FIRST)
Clock
Control Inputs
Data Input
(LAST)
B0
A1
—Address Word—
B1
A0
B2
NC
B3
NC
B4
D11
B5
D10
B6
D9
—DAC Data Word—
B7
D8
B8
D7
B9
D6
B10
D5
B11
D4
B12
D3
B13
D2
(LSB)
B14
D1
B15
D0
(MSB)
NC = Don’t Care.
Reference Inputs
VREFHI: Upper DAC ladder reference voltage input. Allowable range is (V
DD
– 2.5 V) to (V
VREFLO
+2.5 V).
VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is V
SS
to
(V
VREFHI
– 2.5 V).
VOUTA through VOUTD: Four buffered DAC voltage outputs.
Analog Outputs
DIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
DAC8420
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
CLSEL
NC
CLK
SDI
GND
CLR
LD
CS
NC = NO CONNECT
SOL
1
2
3
4
8
7
6
5
(Not to Scale)
DAC-8420
DAC-8420
9
16
15
14
13
12
11
10
NC = NO CONNECT
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
CLSEL
NC
CLK
SDI
GND
CLR
LD
CS
TOP VIEW
相關(guān)PDF資料
PDF描述
DAC8420FP Quad 12-Bit Serial Voltage Output DAC
DAC8420FQ Quad 12-Bit Serial Voltage Output DAC
DAC8420FS Quad 12-Bit Serial Voltage Output DAC
DAC8420EQ Quad 12-Bit Serial Voltage Output DAC
DAC8420EP Quad 12-Bit Serial Voltage Output DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC8426 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V Reference
DAC8426AR 制造商:Rochester Electronics LLC 功能描述:- Bulk
DAC8426AR/883 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter
DAC8426AR/883C 功能描述:數(shù)模轉(zhuǎn)換器- DAC COMPLETE QUAD 8-BIT DAC-LEV.B RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC8426BR 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*