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參數(shù)資料
| 型號(hào)： | DAC8512GBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | % V, Serial Input Complete 12-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, UUC8 |
| 封裝： | DIE-8 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 757K |
| 代理商： | DAC8512GBC |
DAC8512
–4–
REV. A
CLR
t
csh
D11
D10
D9
D8
D7
D6
D5
D3
D4
D1
D2
D0
t
ld2
t
css
t
ld1
t
S
t
dh
t
ds
t
cl
t
ch
t
ldw
t
s
t
clrw
±
1 LSB
ERROR BAND
SDI
CLK
CS
SDI
CLK
FS
ZS
V
OUT
LD
LD
Figure 1. Timing Diagram
DATA
SHIFT
REGISTER
ESD PROTECTION DIODES TO V
DD
AND GND
SDI
CS
CLK
Figure 2. Equivalent Clock Input Logic
Table I. Control-Logic Truth Table
CS
2
CLK
2
CLR
LD
Serial Shift Register Function
DAC Register Function
H
L
L
L
↑
+
H
H
H
H
X
L
H
↑
+
L
X
X
X
X
H
H
H
H
H
H
H
L
↑
+
H
H
H
H
H
↓
–
L
X
H
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with All Zeros
Latched All Zeros
NOTES
l
↑
+ positive logic transition;
↓
– negative logic transition; X = Don’t Care.
2
CS
and CLK are interchangeable.
3
Returning
CS
HIGH avoids an additional “false clock” of serial data input.
4
Do not clock in serial data while
LD
is LOW.
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