參數(shù)資料
型號(hào)： DAC8544I
廠商： Texas Instruments, Inc.
英文描述： QUAD, 16-BIT, RAIL-TO-RAIL VOLTAGE OUTPUT, PARALLEL INTERFACE, DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，16位，軌到軌電壓輸出，并行接口，數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 476K
代理商： DAC8544I
www.ti.com
TIMING CHARACTERISTICS
IOV
= 1.8 V to 5.5 V; V
DD
= 2.7 V to 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications –40
°
C to 85
°
C (unless
otherwise noted)
t
W
1
t
W
5
t
W
2
t
su
1
t
h
1
t
su
3
t
h
3
t
h
4
t
su
2
t
h
2
t
d
1
t
su
4
t
h
2
t
w
4
t
W
3
t
s
±
0.003% of FSR Error Bands
Data Out Valid
Data In Valid
CS
R/W
Data I/O
DB0DB15
LDAC
V
(OUT)
DAC8544
SLAS420–MAY 2004
MIN
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
t
w
1
t
su
1
t
su
2
t
h
1
t
h
2
t
w
2
t
su
3
t
d
1
t
h
3
t
h
4
t
su
4
t
d
2
t
w
3
t
w
4
t
w
5
t
w
6
t
w
7
t
S
Pulse width: CS low for valid write
Setup time: R/W low before CS falling
Setup time: data in valid before CS falling
Hold time: R/W low after CS rising
Hold time: data in valid after CS rising
Pulse width: CS low for valid read
Setup time: R/W high before CS falling
Delay time: data out valid after CS falling
Hold time: R/W high after CS rising
Hold time: data out valid after CS rising
Setup time: LDAC rising after CS falling
Delay time: CS low after LDAC rising
Pulse width: LDAC low
Pulse width: LDAC high
Pulse width: CS high
Pulse width: RST low
Pulse width: RST high
VOUT Settling time (settling time for a full-scale code change)
0
0
10
15
40
30
60
80
10
5
10
50
40
40
80
40
40
20
10
Data Read/Write Timing
4
相關(guān)PDF資料
PDF描述
DAC8551IDGK 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
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DAC8551IDRBT 16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
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DAC8550 制造商:BB 制造商全稱:BB 功能描述:16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER
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