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參數(shù)資料
| 型號(hào)： | DAC8562EP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +5 Volt, Parallel Input Complete 12-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 636K |
| 代理商： | DAC8562EP |
DAC8562
REV. A
–11–
15
16
DGND
10
AGND
12
V
DD
DATA
DAC-8562
13
10μF
0.1μF
–5V
≤
V
O
≤
+5V
+5V
CE
CLR
20
14
REFOUT
V
OUT
R1
10k
R2
12.7k
–2.5V
2
3
4
8
A1
+5V
–5V
1
P2
500
FULL SCALE
ADJUST
R4
23.7k
P1
10k
ZERO SCALE
ADJUST
R3
247k
R5
10k
R6
10k
6
5
A2
7
A1, A2 = 1/2 OP-295
Figure 33. Bipolar Output Operation
Bipolar Output Operation
Although the DAC8562 has been designed for single supply op-
eration, bipolar operation is achievable using the circuit illus-
trated in Figure 33. The circuit uses a single supply, rail-to-rail
OP295 op amp and the DAC’s internal +2.5 V reference to gen-
erate the –2.5 V reference required to level-shift the DAC out-
put voltage. The circuit has been configured to provide an
output voltage in the range –5 V
≤
V
OUT
≤
+5 V and is coded in
complementary offset binary. Although each DAC LSB corre-
sponds to 1 mV, each output LSB has been scaled to 2.44 mV.
Table IV provides the relationship between the digital codes and
output voltage.
The transfer function of the circuit is given by:
V
O
=
1
mV
×
Digital Code
×
R
4
R
1
+
2.5
×
R
4
R
2
and, for the circuit values shown, becomes:
V
O
=
–2.44
mV
×
Digital Code
+
5
V
Table IV. Bipolar Code Table
Hexadecimal Number
in DAC Register
Decimal Number
in DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
–4 9976
–2.44E–3
0
+2.44E–3
+5
To maintain monotonicity and accuracy, R1, R2, R4, R5, and
R6 should be selected to match within 0.01% and must all be of
the same (preferably metal foil) type to assure temperature coef-
ficient matching. Mismatching between R1 and R2 causes offset
and gain errors while an R4 to R1 and R2 mismatch yields gain
errors.
For applications that do not require high accuracy, the circuit il-
lustrated in Figure 34 can also be used to generate a bipolar
output voltage. In this circuit, only one op amp is used and no
potentiometers are used for offset and gain trim The output
voltage is coded in offset binary and is given by:
V
O
=
1
mV
×
Digital Code
×
R
4
R
3
+
R
4
×
1
+
R
2
R
1
–
REFOUT
×
R
2
R
1
For the
±
2 5 V output range and the circuit values shown in the
table, the transfer equation becomes:
V
O
=
1.22
mV
×
Digital Code
– 2.5
V
Similarly, for the
±
5 V output range, the transfer equation be-
comes:
V
O
=
2.44
mV
×
Digital Code
– 5
V
Note that, for
±
5 V output voltage operation, R5 is required as a
pull-down for REFOUT. Or, REFOUT can be buffered by an
op amp configured as a follower that can source and sink cur-
rent.
15
16
DATA
DAC-8562
13
CE
CLR
DGND
10
AGND
12
V
DD
0.1μF
+5V
20
14
REFOUT
V
OUT
R1
R5
4.99k
A1 = 1/2 OP-295
R4
R3
R2
2
3
4
8
A1
+5V
–5V
1
V
O
V
RANGE
±2.5V
±5V
R1
10k
10k
R2
10k
20k
R3
10k
10k
R4
15.4k + 274
43.2k + 499
Figure 34. Bipolar Output Operation Without
Trim Version 1
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