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參數(shù)資料
| 型號(hào)： | DAC908U/1K |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, 8 BITS INPUT LOADING, 0.03 us SETTLING TIME, 8-BIT DAC, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 180K |
| 代理商： | DAC908U/1K |
DAC908
14
FIGURE 8. External Reference Configuration.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
High (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1
F capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1M
) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.1V to 1.25V).
DIGITAL INPUTS
The digital inputs, D0 (LSB) through D7 (MSB) of the
DAC908 accept standard positive binary coding. The digital
input word is latched into a master-slave latch with the rising
edge of the clock. The DAC output becomes updated with
the following rising clock edge (refer to the specification
table and timing diagram for details). The best performance
will be achieved with a 50% clock duty cycle, however, the
duty cycle may vary as long as the timing specifications are
met. Additionally, the setup and hold times may be chosen
within their specified limits.
All digital inputs are CMOS compatible. The logic thresh-
olds depend on the applied digital supply voltage such that
they are set to approximately half the supply voltage;
Vth = +VD/2 (
±20% tolerance). The DAC908 is designed to
operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE
The DAC908 features a power-down function which can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic
High to the PD pin will initiate the power-down mode, while
a logic Low enables normal operation. When left uncon-
nected, an internal active pull-down circuit will enable the
normal operation of the converter.
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
The DAC908 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+V
A)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1uF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. There-
fore they should be located as close as physically possible to
those device leads. Whenever possible, the capacitors should
be located immediately under each pair of supply/ground
pins on the reverse side of the pc board. This layout ap-
proach will minimize the parasitic inductance of component
leads and pcb runs.
R
SET
+5V
External
Reference
I
REF =
V
REF
R
SET
DAC908
C
COMPEXT
0.1
F
C
COMP
400pF
+1.24V Ref.
INT/EXT
FSA
BW
+5V
+V
A
REF
IN
Current
Sources
Ref
Control
Amp
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