參數(shù)資料
型號： DAC908U/1K
元件分類： DAC
英文描述： PARALLEL, 8 BITS INPUT LOADING, 0.03 us SETTLING TIME, 8-BIT DAC, PDSO28
封裝： SOP-28
文件頁數(shù)： 8/15頁
文件大小： 180K
代理商： DAC908U/1K
DAC908
2
SPECIFICATIONS
At T
A = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50 doubly terminated, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
DAC908U/E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
8
Bits
Output Update Rate (fCLOCK)
4.5V to 5.5V
165
200
MSPS
Output Update Rate
2.7V to 3.3V
125
165
MSPS
Full Specified Temperature Range, Operating
Ambient, TA
–40
+85
°C
STATIC ACCURACY(1)
TA = +25°C
Differential Nonlinearity (DNL)
fCLOCK = 25MSPS, fOUT = 1.0MHz
–0.5
±0.25
+0.5
LSB
Integral Nonlinearity (INL)
–0.5
±0.25
+0.5
LSB
DYNAMIC PERFORMANCE
TA = +25°C
Spurious Free Dynamic Range (SFDR)
To Nyquist
fOUT = 1.0MHz, fCLOCK = 25MSPS
64
70
dBc
fOUT = 2.1MHz, fCLOCK = 50MSPS
69
dBc
fOUT = 5.04MHz, fCLOCK = 50MSPS
67
dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS
67
dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS
61
dBc
fOUT = 25.3MHz, fCLOCK = 125MSPS
57
dBc
fOUT = 41.5MHz, fCLOCK = 125MSPS
51
dBc
fOUT = 27.4MHz, fCLOCK = 165MSPS
58
dBc
fOUT = 54.8MHz, fCLOCK = 165MSPS
52
dBc
Spurious Free Dynamic Range within a Window
fOUT = 2.1MHz, fCLOCK = 50MSPS
2MHz Span
70
dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS
4MHz Span
69
dBc
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS
–72
dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS
–66
dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS
–60
dBc
Output Settling Time(2)
to 0.1%
30
ns
Output Rise Time(2)
10% to 90%
2
ns
Output Fall Time(2)
10% to 90%
2
ns
Glitch Impulse
3
pV-s
DC-ACCURACY
Full-Scale Output Range(3)(FSR)
All Bits High, IOUT
2.0
20.0
mA
Output Compliance Range
–1.0
+1.25
V
Gain Error
With Internal Reference
–10
±1
+10
%FSR
Gain Error
With External Reference
–10
±2
+10
%FSR
Gain Drift
With Internal Reference
±120
ppmFSR/
°C
Offset Error
With Internal Reference
–0.025
+0.025
%FSR
Offset Drift
With Internal Reference
±0.1
ppmFSR/
°C
Power Supply Rejection, +VA
–0.2
+0.2
%FSR/V
Power Supply Rejection, +VD
–0.025
+0.025
%FSR/V
Output Noise
IOUT = 20mA, RLOAD = 50
50
pA/
√Hz
Output Resistance
200
k
Output Capacitance
IOUT, IOUT to Ground
12
pF
REFERENCE
Reference Voltage
+1.24
V
Reference Tolerance
±5%
Reference Voltage Drift
±50
ppmFSR/
°C
Reference Output Current
10
A
Reference Input Resistance
1M
Reference Input Compliance Range
0.1
1.25
V
Reference Small Signal Bandwidth(4)
1.3
MHz
DIGITAL INPUTS
Logic Coding
Straight Binary
Latch Command
Rising Edge of Clock
Logic High Voltage, VIH
+VD = +5V
3.5
5
V
Logic Low Voltage, VIL
+VD = +5V
0
1.2
V
Logic High Voltage, VIH
+VD = +3V
2
3
V
Logic Low Voltage, VIL
+VD = +3V
0
0.8
V
Logic High Current, IIH(5)
+VD = +5V
±20
A
Logic Low Current, IIL
+VD = +5V
±20
A
Input Capacitance
5pF
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