參數(shù)資料
型號(hào)： DC1009A-B
廠商： Linear Technology
文件頁(yè)數(shù)： 10/30頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2488
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1009A Design File
DC1009A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 6.9
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2488
已供物品： 板
相關(guān)產(chǎn)品： LTC2488CDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488IDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488CDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488IDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488
18
2488fa
APPLICATIONS INFORMATION
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 7).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be oating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (FO is tied LOW),
the rst rising edge of SCK occurs 12μs (tEOCTEST = 12μs)
after the falling edge of CS. If FO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the rst rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH any time between the 1st rising edge and
the 24th falling edge of SCK (see Figure 8). On the ris-
ing edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
VCC
FO
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2488
3-WIRE
SPI INTERFACE
REF+
REF–
CH0
CH1
CH2
CH3
COM
SDO
12
1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1μF
10μF
CS
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2488 F06
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
1
0
EN
SGL
A2
A1
A0
ODD
BIT 0
DON'T CARE
MSB
SIG
“0”
12
3
4
5
6
7
8
9
19
20
21
22
23
24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Figure 6. External Serial Clock, 3-Wire Operation (CS = 0)
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DC100A10 功能描述:固態(tài)繼電器-工業(yè)安裝 SSR DC OUTPUT 10A 90-140VAC RoHS:否 制造商:Crydom 控制電壓范圍:4 VDC to 32 VDC 負(fù)載電壓額定值:7 VDC to 72 VDC 負(fù)載電流額定值:160 A 觸點(diǎn)形式: 輸出設(shè)備:SSR 安裝風(fēng)格:Panel
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