參數資料
型號: DC1009A-B
廠商: Linear Technology
文件頁數: 6/30頁
文件大小: 0K
描述: BOARD DELTA SIGMA ADC LTC2488
軟件下載: QuikEval System
設計資源: DC1009A Design File
DC1009A Schematic
標準包裝: 1
系列: Easy Drive™, QuikEval™
ADC 的數量: 1
位數: 16
采樣率(每秒): 6.9
數據接口: MICROWIRE?,串行,SPI?
已用 IC / 零件: LTC2488
已供物品:
相關產品: LTC2488CDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488IDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488CDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488IDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2488
14
2488fa
APPLICATIONS INFORMATION
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the fO pin from HIGH to LOW at the completion
of a conversion. This signal may be used as an interrupt for
an external microcontroller. Bit 23 (EOC) can be captured
on the rst rising edge of SCK. Bit 22 is shifted out of the
device on the rst falling edge of SCK. The nal data bit
(Bit 0) is shifted out on the on the falling edge of the 23rd
SCK and may be latched on the rising edge of the 24th SCK
pulse. On the falling edge of the 24th SCK pulse, SDO goes
HIGH indicating the initiation of a new conversion cycle.
This bit serves as EOC (Bit 23) for the next conversion
cycle. Table 2 summarizes the output data format.
As long as the voltage on the IN+ and INpins remains be-
tween –0.3V and VCC + 0.3V (absolute maximum operating
range) a conversion result is generated for any differential
input voltage VIN from –FS = –0.5 VREF to +FS = 0.5
VREF. For differential input voltages greater than +FS, the
conversion result is clamped to the value corresponding to
+FS + 1LSB. For differential input voltages below –FS, the
conversion result is clamped to the value –FS – 1LSB.
INPUT DATA FORMAT
The LTC2488 serial input word is 8 bits long. The input
bits (SGL, ODD, A2, A1, A0) are used to select the input
channel.
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2488 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
MSB
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
SIG
BIT 21
“0”
BIT 22
BIT 23
1
0
EN
SGL
A2
A1
A0
ODD
BIT 10
BIT 9
BIT 0
12
3
4
5
6
7
8
9
10
11
12
13
14
24
DON'T CARE
Figure 3. Channel Selection and Data Output Timing
Table 2. Output Data Format
Differential Input Voltage
VIN*
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
Bit 19
Bit 18
Bit 17
Bit 4
LSB
Bits 3 to 0
Always 0
VIN* ≥ 0.5 VREF**
0
1
0
0
0000
0.5 VREF** – 1LSB
0
1
0
1
1
0000
0.25 VREF**
0
1
0
1
0
0
0000
0.25 VREF** – 1LSB
0
1
0
1
1
0000
0
1
0
0
0000
–1LSB
0
1
1
0000
–0.25 VREF**
0
1
0
0
0000
–0.25 VREF** – 1LSB
0
1
0
1
1
0000
–0.5 VREF**
0
1
0
0
0000
VIN* < –0.5 VREF**
0
1
1
0000
*The differential input voltage VIN = IN+ – IN. **The differential reference voltage VREF = REF+ – REF.
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