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參數(shù)資料
| 型號(hào)： | DC1009A-B |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/30頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2488 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC1009A Design File DC1009A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.9 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2488 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2488CDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN LTC2488IDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN LTC2488CDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN LTC2488IDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN |
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LTC2488
13
2488fa
APPLICATIONS INFORMATION
The serial clock pin (SCK) can be congured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply oating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Specic
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB rst) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once the
conversion is complete, if CS is brought LOW, EOC will be
driven LOW indicating the conversion is complete and the
result is ready to be shifted out of the device.
Chip Select (CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
CS HIGH any time between the rst and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input
channel. Data is shifted into the device during the data
output/input state on the rising edge of SCK while CS is
low.
OUTPUT DATA FORMAT
The LTC2488 serial output stream is 24 bits long. The
rst bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB rst. The
remaining 4 bits are always LOW.
Bit 23 (rst output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This
bit is HIGH during the conversion cycle, goes LOW once
the conversion is complete, and is HIGH-Z when CS is
HIGH.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If the selected input (VIN = IN+ – IN–) is
greater than or equal to 0V, this bit is HIGH. If VIN < 0,
this bit is LOW.
Bit 20 (fourth output bit) is the most signicant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2488 Status Bits
Input Range
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 VREF
0011
0V ≤ VIN < 0.5 VREF
0010
–0.5 VREF ≤ VIN < 0V
0001
VIN < –0.5 VREF
0000
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB rst.
Bit 4 is the least signicant bit (LSB16).
Bits 3 to 0 are always LOW.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DC1009A-C | 功能描述:BOARD DELTA SIGMA ADC LTC2486 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:Easy Drive™, QuikEval™ 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| DC100A10 | 功能描述:固態(tài)繼電器-工業(yè)安裝 SSR DC OUTPUT 10A 90-140VAC RoHS:否 制造商:Crydom 控制電壓范圍:4 VDC to 32 VDC 負(fù)載電壓額定值:7 VDC to 72 VDC 負(fù)載電流額定值:160 A 觸點(diǎn)形式: 輸出設(shè)備:SSR 安裝風(fēng)格:Panel |
| DC100A10C | 功能描述:固態(tài)繼電器-工業(yè)安裝 SSR DC OUTPUT 10A 90-140VAC RoHS:否 制造商:Crydom 控制電壓范圍:4 VDC to 32 VDC 負(fù)載電壓額定值:7 VDC to 72 VDC 負(fù)載電流額定值:160 A 觸點(diǎn)形式: 輸出設(shè)備:SSR 安裝風(fēng)格:Panel |
| DC100A20 | 功能描述:固態(tài)繼電器-工業(yè)安裝 SSR DC OUTPUT 20A 90-140VAC RoHS:否 制造商:Crydom 控制電壓范圍:4 VDC to 32 VDC 負(fù)載電壓額定值:7 VDC to 72 VDC 負(fù)載電流額定值:160 A 觸點(diǎn)形式: 輸出設(shè)備:SSR 安裝風(fēng)格:Panel |
| DC100A20C | 功能描述:固態(tài)繼電器-工業(yè)安裝 SSR DC OUTPUT 20A 90-140VAC RoHS:否 制造商:Crydom 控制電壓范圍:4 VDC to 32 VDC 負(fù)載電壓額定值:7 VDC to 72 VDC 負(fù)載電流額定值:160 A 觸點(diǎn)形式: 輸出設(shè)備:SSR 安裝風(fēng)格:Panel |
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